Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering
As gate-all-around nanosheet transistors (GAA NSFETs) replacing current FinFETs for their superior gate control capabilities, it needs various performance optimizations for better transistor and circuit benefits. In this paper, special optimizations to source/drain (S/D) doping engineering including...
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2025-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10845751/ |
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| author | Xuexiang Zhang Qingkun Li Lei Cao Qingzhu Zhang Renjie Jiang Peng Wang Jiaxin Yao Huaxiang Yin |
| author_facet | Xuexiang Zhang Qingkun Li Lei Cao Qingzhu Zhang Renjie Jiang Peng Wang Jiaxin Yao Huaxiang Yin |
| author_sort | Xuexiang Zhang |
| collection | DOAJ |
| description | As gate-all-around nanosheet transistors (GAA NSFETs) replacing current FinFETs for their superior gate control capabilities, it needs various performance optimizations for better transistor and circuit benefits. In this paper, special optimizations to source/drain (S/D) doping engineering including spacer bottom footing (SBF) and refining the lightly doped drain (LDD) implantation process are explored to enhance both fabricated complementary metal oxide semiconductor (CMOS) NSFETs and their 6T-SRAM cells. The experimental results demonstrate that the optimal SBF width increased the static noise margin (SNM) of the SRAM cells by 14.9%, while significantly reducing static power consumption for the balance performance between the NMOS and PMOS and reduced current in all leakage paths of SRAM. Moreover, the LDD optimization significantly reduced off-state leakage current (<inline-formula> <tex-math notation="LaTeX">$\rm I_{\mathrm {off}}$ </tex-math></inline-formula>) for both NMOS and PMOS due to the reductions of peak electric field in overlap region between the S/D and the channel, leading to a 9.5% improvement in SNM and a substantial reduction in static power consumption. These results indicate that the optimization to S/D doping engineering may achieve substantial performance gains in both the GAA CMOS transistors and the SRAM cells. |
| format | Article |
| id | doaj-art-170f348a0a03424e94c2d1d9ed4f740b |
| institution | Kabale University |
| issn | 2168-6734 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-170f348a0a03424e94c2d1d9ed4f740b2025-02-04T00:00:33ZengIEEEIEEE Journal of the Electron Devices Society2168-67342025-01-0113869210.1109/JEDS.2025.353143210845751Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping EngineeringXuexiang Zhang0https://orcid.org/0009-0002-7459-7826Qingkun Li1https://orcid.org/0009-0002-4764-7541Lei Cao2https://orcid.org/0000-0002-0755-6488Qingzhu Zhang3https://orcid.org/0000-0003-0035-0652Renjie Jiang4https://orcid.org/0009-0001-7072-0359Peng Wang5Jiaxin Yao6https://orcid.org/0000-0002-7668-4811Huaxiang Yin7https://orcid.org/0000-0001-8066-6002Key Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaAs gate-all-around nanosheet transistors (GAA NSFETs) replacing current FinFETs for their superior gate control capabilities, it needs various performance optimizations for better transistor and circuit benefits. In this paper, special optimizations to source/drain (S/D) doping engineering including spacer bottom footing (SBF) and refining the lightly doped drain (LDD) implantation process are explored to enhance both fabricated complementary metal oxide semiconductor (CMOS) NSFETs and their 6T-SRAM cells. The experimental results demonstrate that the optimal SBF width increased the static noise margin (SNM) of the SRAM cells by 14.9%, while significantly reducing static power consumption for the balance performance between the NMOS and PMOS and reduced current in all leakage paths of SRAM. Moreover, the LDD optimization significantly reduced off-state leakage current (<inline-formula> <tex-math notation="LaTeX">$\rm I_{\mathrm {off}}$ </tex-math></inline-formula>) for both NMOS and PMOS due to the reductions of peak electric field in overlap region between the S/D and the channel, leading to a 9.5% improvement in SNM and a substantial reduction in static power consumption. These results indicate that the optimization to S/D doping engineering may achieve substantial performance gains in both the GAA CMOS transistors and the SRAM cells.https://ieeexplore.ieee.org/document/10845751/Gate-all-around nanosheet transistor (GAA NSFET)source/drain (S/D) dopingspacerlightly doped drain (LDD)6T static random-access memory (6T-SRAM) |
| spellingShingle | Xuexiang Zhang Qingkun Li Lei Cao Qingzhu Zhang Renjie Jiang Peng Wang Jiaxin Yao Huaxiang Yin Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering IEEE Journal of the Electron Devices Society Gate-all-around nanosheet transistor (GAA NSFET) source/drain (S/D) doping spacer lightly doped drain (LDD) 6T static random-access memory (6T-SRAM) |
| title | Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering |
| title_full | Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering |
| title_fullStr | Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering |
| title_full_unstemmed | Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering |
| title_short | Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering |
| title_sort | performance optimization of fabricated nanosheet gaa cmos transistors and 6t sram cells via source drain doping engineering |
| topic | Gate-all-around nanosheet transistor (GAA NSFET) source/drain (S/D) doping spacer lightly doped drain (LDD) 6T static random-access memory (6T-SRAM) |
| url | https://ieeexplore.ieee.org/document/10845751/ |
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