Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering

Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering

As gate-all-around nanosheet transistors (GAA NSFETs) replacing current FinFETs for their superior gate control capabilities, it needs various performance optimizations for better transistor and circuit benefits. In this paper, special optimizations to source/drain (S/D) doping engineering including...

Full description

Saved in:
Bibliographic Details
Main Authors: Xuexiang Zhang, Qingkun Li, Lei Cao, Qingzhu Zhang, Renjie Jiang, Peng Wang, Jiaxin Yao, Huaxiang Yin
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Gate-all-around nanosheet transistor (GAA NSFET)
source/drain (S/D) doping
spacer
lightly doped drain (LDD)
6T static random-access memory (6T-SRAM)
Online Access:https://ieeexplore.ieee.org/document/10845751/
Tags: Add Tag
No Tags, Be the first to tag this record!

Internet

https://ieeexplore.ieee.org/document/10845751/

Similar Items