High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions
The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by artificial intelligence and machine learning (AI/ML). This article reviews these advanced packaging technologies and emphasizes criti...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10767590/ |
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| author | Shenggao Li Mu-Shan Lin Wei-Chih Chen Chien-Chun Tsai |
| author_facet | Shenggao Li Mu-Shan Lin Wei-Chih Chen Chien-Chun Tsai |
| author_sort | Shenggao Li |
| collection | DOAJ |
| description | The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by artificial intelligence and machine learning (AI/ML). This article reviews these advanced packaging technologies and emphasizes critical design considerations for high-bandwidth chiplet interconnects, which are vital for efficient integration. We address challenges related to bandwidth density, energy efficiency, electromigration, power integrity, and signal integrity. To avoid power overhead, the chiplet interconnect architecture is designed to be as simple as possible, employing a parallel data bus with forwarded clocks. However, achieving highyield manufacturing and robust performance still necessitates significant efforts in design and technology co-optimization. Despite these challenges, the semiconductor industry is poised for continued growth and innovation, driven by the possibilities unlocked by a robust chiplet ecosystem and novel 3D-IC design methodologies. |
| format | Article |
| id | doaj-art-fc1d69a7edd440bfaad51ac7754591f4 |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-fc1d69a7edd440bfaad51ac7754591f42025-01-25T00:03:22ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-01435136410.1109/OJSSCS.2024.350669410767590High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and SolutionsShenggao Li0https://orcid.org/0000-0001-9296-1121Mu-Shan Lin1https://orcid.org/0000-0002-1268-1013Wei-Chih Chen2Chien-Chun Tsai3Design and Technology Platform, Taiwan Semiconductor Manufacturing Company Ltd., San Jose, CA, USADesign and Technology Platform, Taiwan Semiconductor Manufacturing Company Ltd., San Jose, CA, USADesign and Technology Platform, Taiwan Semiconductor Manufacturing Company Ltd., San Jose, CA, USADesign and Technology Platform, Taiwan Semiconductor Manufacturing Company Ltd., San Jose, CA, USAThe demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by artificial intelligence and machine learning (AI/ML). This article reviews these advanced packaging technologies and emphasizes critical design considerations for high-bandwidth chiplet interconnects, which are vital for efficient integration. We address challenges related to bandwidth density, energy efficiency, electromigration, power integrity, and signal integrity. To avoid power overhead, the chiplet interconnect architecture is designed to be as simple as possible, employing a parallel data bus with forwarded clocks. However, achieving highyield manufacturing and robust performance still necessitates significant efforts in design and technology co-optimization. Despite these challenges, the semiconductor industry is poised for continued growth and innovation, driven by the possibilities unlocked by a robust chiplet ecosystem and novel 3D-IC design methodologies.https://ieeexplore.ieee.org/document/10767590/3Dblox3D-ICadvanced packagingartificial intelligence (AI) and computechiplet integrationenergy efficiency |
| spellingShingle | Shenggao Li Mu-Shan Lin Wei-Chih Chen Chien-Chun Tsai High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions IEEE Open Journal of the Solid-State Circuits Society 3Dblox 3D-IC advanced packaging artificial intelligence (AI) and compute chiplet integration energy efficiency |
| title | High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions |
| title_full | High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions |
| title_fullStr | High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions |
| title_full_unstemmed | High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions |
| title_short | High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions |
| title_sort | high bandwidth chiplet interconnects for advanced packaging technologies in ai ml applications challenges and solutions |
| topic | 3Dblox 3D-IC advanced packaging artificial intelligence (AI) and compute chiplet integration energy efficiency |
| url | https://ieeexplore.ieee.org/document/10767590/ |
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