SCALABLE LOGIC BIST DESIGN AND ANALYSIS FOR ENHANCED TESTING OF COMBINATIONAL CIRCUITS
The paper introduces a scalable Logic Built-In Self-Test (BIST) approach for combinational circuits, utilizing a Bit Swapping Linear Feedback Shift Register (BS-LFSR) as the test pattern generator. Unlike conventional Linear Feedback Shift Registers (LFSRs) that lead to increased dynamic power dissi...
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| Main Authors: | Suhas Shirol, Rajashekhar Shettar, Ramakrishna S, Vijay H M |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
University of Kragujevac
2025-06-01
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| Series: | Proceedings on Engineering Sciences |
| Subjects: | |
| Online Access: | https://pesjournal.net/journal/v7-n2/69.pdf |
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