All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
Abstract Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of test complexity and cost. An all‐digital...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2021-01-01
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| Series: | IET Circuits, Devices and Systems |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cds2.12000 |
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