Toward Fine-Grained Partitioning of Low-Level SRAM Caches for Emerging 3D-IC Designs

Toward Fine-Grained Partitioning of Low-Level SRAM Caches for Emerging 3D-IC Designs

Scaling on-chip memory capacity is one of the primary approaches to mitigate memory wall bottlenecks. Various 2.5-D/3-D integration schemes, leveraging novel partitioning, are being actively explored to improve system performance. However, fine-grained functional partitioning of memory macros is not...

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Bibliographic Details
Main Authors: Sudipta Das, Bhawana Kumari, Siva Satyendra Sahoo, Yukai Chen, James Myers, Dragomir Milojevic, Dwaipayan Biswas, Julien Ryckaert
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Subjects:
3-D integrated circuit (3D-IC)
ARM
array under CMOS (AuC)
mobile computing
monolithic integration
partitioning
Online Access:https://ieeexplore.ieee.org/document/10695147/
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https://ieeexplore.ieee.org/document/10695147/

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