Demonstration of Vertically Stacked ZnO/Te Complementary Field‐Effect Transistor

Demonstration of Vertically Stacked ZnO/Te Complementary Field‐Effect Transistor

Abstract The complementary field‐effect transistor (CFET) structure is a highly area‐efficient technology. However, their fabrication entails highly complex integration processes using wafer transfer or recrystallization, which has been limiting further development. In this paper, an alternative met...

Full description

Saved in:
Bibliographic Details
Main Authors: Kiyung Kim, Minjae Kim, Yongsu Lee, Hae‐Won Lee, Jae Hyeon Jun, Jun‐Hyeok Choi, Seongbeen Yoon, Hyeon‐Jun Hwang, Byoung Hun Lee
Format: Article
Language:English
Published: Wiley-VCH 2025-08-01
Series:Advanced Electronic Materials
Subjects:
complementary field‐effect transistors (CFETs)
integration process
logic gate
tellurium (Te)
zinc oxide (ZnO)
Online Access:https://doi.org/10.1002/aelm.202500031
Tags: Add Tag
No Tags, Be the first to tag this record!

Internet

https://doi.org/10.1002/aelm.202500031

Similar Items