Fast-Read Storage Performance by Thyristor Operation in 3-D Flash Memory
In this work, we report the fast-read storage performance of thyristor operation in 3D flash memory. By forming a pseudo N+/P/N/P+ structure with the word line (WL) bias of 3D string cells, thyristor operation with steep switching characteristics and a high on-current can be obtained. It is known th...
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2024-01-01
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| author | Tomoya Sanuki Hideto Horii Takashi Maeda |
| author_facet | Tomoya Sanuki Hideto Horii Takashi Maeda |
| author_sort | Tomoya Sanuki |
| collection | DOAJ |
| description | In this work, we report the fast-read storage performance of thyristor operation in 3D flash memory. By forming a pseudo N+/P/N/P+ structure with the word line (WL) bias of 3D string cells, thyristor operation with steep switching characteristics and a high on-current can be obtained. It is known that there is a strong cell-to-cell interference effect in thyristor operation, and in previous report (Horii et al., 2020), we have suggested novel WL bias conditions, referred to as the wide barrier mode, that can suppress the cell-to-cell interference effect. In order to evaluate the advantages of thyristor operation in 3D flash memory further, we report for the first time the several cell characteristics and reliability issues of thyristor operation required for the actual usage of storage products. (1) We demonstrate excellent cell characteristics of a wide programmed Vth window and sufficient program slope values in thyristor operation, which are indispensable for realizing multi-level cells. (2) Cell characteristics of thyristor operation exhibit hysteresis when sweeping in the WL direction but not in the bit line (BL) direction, which is essential for determining the read operating waveform. (3) Our proposed new WL biasing scheme to suppress the cell-to-cell interference effect is described with a more detailed dependence on adjacent cells and its effect on the on-current. We show that a high on-current can still be achieved even with highly stacked WL of approximately 100 layers. (4) In terms of reliability issues, thyristor operation exhibits a sufficient margin against read cycle stress with minimal change in the cell Vth even after 2 million read cycles. Thyristor operation can be applied to storage products even in read-intensive applications. (5) We also describe storage performance, including read latency and bandwidth, for SLC and QLC mode in memory arrays with highly stacked WL of approximately 100 layers. Thyristor operation of 3D flash memory is a strong candidate for future high-speed storage products, as it can significantly improve read latency and program throughput. |
| format | Article |
| id | doaj-art-e94ec1ae3b284c96bb13c147489c4ccb |
| institution | Kabale University |
| issn | 2168-6734 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-e94ec1ae3b284c96bb13c147489c4ccb2025-01-28T00:00:45ZengIEEEIEEE Journal of the Electron Devices Society2168-67342024-01-011271071610.1109/JEDS.2024.343888610624679Fast-Read Storage Performance by Thyristor Operation in 3-D Flash MemoryTomoya Sanuki0https://orcid.org/0000-0003-2450-3684Hideto Horii1Takashi Maeda2https://orcid.org/0009-0003-9708-1694Frontier Technology R&D Institute, Kioxia Corporation, Yokkaichi, Mie, JapanFrontier Technology R&D Institute, Kioxia Corporation, Yokohama, Kanagawa, JapanFrontier Technology R&D Institute, Kioxia Corporation, Yokohama, Kanagawa, JapanIn this work, we report the fast-read storage performance of thyristor operation in 3D flash memory. By forming a pseudo N+/P/N/P+ structure with the word line (WL) bias of 3D string cells, thyristor operation with steep switching characteristics and a high on-current can be obtained. It is known that there is a strong cell-to-cell interference effect in thyristor operation, and in previous report (Horii et al., 2020), we have suggested novel WL bias conditions, referred to as the wide barrier mode, that can suppress the cell-to-cell interference effect. In order to evaluate the advantages of thyristor operation in 3D flash memory further, we report for the first time the several cell characteristics and reliability issues of thyristor operation required for the actual usage of storage products. (1) We demonstrate excellent cell characteristics of a wide programmed Vth window and sufficient program slope values in thyristor operation, which are indispensable for realizing multi-level cells. (2) Cell characteristics of thyristor operation exhibit hysteresis when sweeping in the WL direction but not in the bit line (BL) direction, which is essential for determining the read operating waveform. (3) Our proposed new WL biasing scheme to suppress the cell-to-cell interference effect is described with a more detailed dependence on adjacent cells and its effect on the on-current. We show that a high on-current can still be achieved even with highly stacked WL of approximately 100 layers. (4) In terms of reliability issues, thyristor operation exhibits a sufficient margin against read cycle stress with minimal change in the cell Vth even after 2 million read cycles. Thyristor operation can be applied to storage products even in read-intensive applications. (5) We also describe storage performance, including read latency and bandwidth, for SLC and QLC mode in memory arrays with highly stacked WL of approximately 100 layers. Thyristor operation of 3D flash memory is a strong candidate for future high-speed storage products, as it can significantly improve read latency and program throughput.https://ieeexplore.ieee.org/document/10624679/3D flash memorythyristor operationfast-read storage performancehigh-speedSLCQLC |
| spellingShingle | Tomoya Sanuki Hideto Horii Takashi Maeda Fast-Read Storage Performance by Thyristor Operation in 3-D Flash Memory IEEE Journal of the Electron Devices Society 3D flash memory thyristor operation fast-read storage performance high-speed SLC QLC |
| title | Fast-Read Storage Performance by Thyristor Operation in 3-D Flash Memory |
| title_full | Fast-Read Storage Performance by Thyristor Operation in 3-D Flash Memory |
| title_fullStr | Fast-Read Storage Performance by Thyristor Operation in 3-D Flash Memory |
| title_full_unstemmed | Fast-Read Storage Performance by Thyristor Operation in 3-D Flash Memory |
| title_short | Fast-Read Storage Performance by Thyristor Operation in 3-D Flash Memory |
| title_sort | fast read storage performance by thyristor operation in 3 d flash memory |
| topic | 3D flash memory thyristor operation fast-read storage performance high-speed SLC QLC |
| url | https://ieeexplore.ieee.org/document/10624679/ |
| work_keys_str_mv | AT tomoyasanuki fastreadstorageperformancebythyristoroperationin3dflashmemory AT hidetohorii fastreadstorageperformancebythyristoroperationin3dflashmemory AT takashimaeda fastreadstorageperformancebythyristoroperationin3dflashmemory |