Efficient 22 nm GNRFET PTLA using low power trimode technique for high speed processor
Abstract This paper introduces a new low-power pass transistor logic adder (PTLA) design utilizing 22 nm GNRFET (Graphene Nano Ribbon Field Effect Transistor) technology to enhance computing performance. The PTLA is designed with pass transistor logic that helps in optimization of transistor count....
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Nature Portfolio
2025-04-01
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| Series: | Scientific Reports |
| Subjects: | |
| Online Access: | https://doi.org/10.1038/s41598-025-91656-y |
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| Summary: | Abstract This paper introduces a new low-power pass transistor logic adder (PTLA) design utilizing 22 nm GNRFET (Graphene Nano Ribbon Field Effect Transistor) technology to enhance computing performance. The PTLA is designed with pass transistor logic that helps in optimization of transistor count. By effectively integrating PTLA with a low-power trimode technique, the proposed design optimizes key metrics such as power consumption, delay, and area. The innovative use of graphene based GNRFET ensures high carrier mobility and temperature resilience, while the trimode technique dynamically manages operational states for improved energy efficiency. The performance of two distinct configurations, 24T PTLA and 21T PTLA, has been evaluated under varying temperature and voltage conditions. Process voltage temperature (PVT) and Monte Carlo analysis validate the proposed circuits’ adaptability and reliability, showcasing substantial improvement in power-delay product (PDP) and leakage current. These advancements establish the designs as ideal candidates for AI-enabled devices and edge computing applications, where low power and high speed are critical parameters. Extensive Synopsys HSPICE simulations have been employed for performance optimization, demonstrating the robustness of the designs for next generation digital computing technologies. The 24T PTLA structure reduces the power by 99.9% and PDP by 99.5% compared to conventional CMOS, hybrid and transmission gate logic, which proves the highly energy-efficient nature of the circuit. The 21T PTLA design enhances delay stability by 99.6% and reduces leakage current by 99.8%, which ensures dependable performance under diversified conditions. |
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| ISSN: | 2045-2322 |