Efficient 22 nm GNRFET PTLA using low power trimode technique for high speed processor

Efficient 22 nm GNRFET PTLA using low power trimode technique for high speed processor

Abstract This paper introduces a new low-power pass transistor logic adder (PTLA) design utilizing 22 nm GNRFET (Graphene Nano Ribbon Field Effect Transistor) technology to enhance computing performance. The PTLA is designed with pass transistor logic that helps in optimization of transistor count....

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Bibliographic Details
Main Authors: Sneha Arora, Suman Lata Tripathi, Inung Wijayanto, Sobhit Saxena
Format: Article
Language:English
Published: Nature Portfolio 2025-04-01
Series:Scientific Reports
Subjects:
Pass transistor logic
Trimode technique
Graphene nano ribbon FET
Synopsys HSPICE
Power delay product
Hybrid full adder (HFA)
Online Access:https://doi.org/10.1038/s41598-025-91656-y
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https://doi.org/10.1038/s41598-025-91656-y

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