New scan compression approach to reduce the test data volume
Abstract The test data volume (TDV) increases with increased target compression in scan compression and adds to the test cost. Increased TDV is the result of a dependency across scan flip‐flops (SFFs) that resulted from compression architecture, which is absent in scan mode. The SFFs have uncompress...
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Wiley
2021-07-01
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| Series: | IET Computers & Digital Techniques |
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| Online Access: | https://doi.org/10.1049/cdt2.12020 |
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| author | Pralhadrao V. Shantagiri Rohit Kapur Chandrasekar Shastry |
| author_facet | Pralhadrao V. Shantagiri Rohit Kapur Chandrasekar Shastry |
| author_sort | Pralhadrao V. Shantagiri |
| collection | DOAJ |
| description | Abstract The test data volume (TDV) increases with increased target compression in scan compression and adds to the test cost. Increased TDV is the result of a dependency across scan flip‐flops (SFFs) that resulted from compression architecture, which is absent in scan mode. The SFFs have uncompressible values logic‐0 and logic‐1 in many or most of the patterns contribute to the TDV. In the proposed new scan compression (NSC) architecture, SFFs are analysed from Automatic Test Pattern Generation (ATPG) patterns generated in a scan mode. The identification of SFFs to be moved out of the compression architecture is carried out based on the NSC. The method includes a ranking of SFFs based on the specified values present in the test patterns. The SFFs having higher specified values are moved out of the compression architecture and placed in the outside scan chain. The NSC is the combination of scan compression and scan mode. This method decides the percentage (%) of SFFs to be moved out of compression architecture and is less than 0.5% of the total SFFs present in the design to achieve a better result. The NSC reduces dependencies across the SFFs present in the test compression architecture. It reduces the TDV and test application time. The results show a significant reduction in the TDV up to 78.14% for the same test coverage. |
| format | Article |
| id | doaj-art-e3422a96272f4235ad4933e3af192bf9 |
| institution | Kabale University |
| issn | 1751-8601 1751-861X |
| language | English |
| publishDate | 2021-07-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj-art-e3422a96272f4235ad4933e3af192bf92025-02-03T01:29:41ZengWileyIET Computers & Digital Techniques1751-86011751-861X2021-07-0115425126210.1049/cdt2.12020New scan compression approach to reduce the test data volumePralhadrao V. Shantagiri0Rohit Kapur1Chandrasekar Shastry2Department of Computer Science Jain University Bangalore IndiaDepartment of Computer Science Research Guide Jain University Bangalore IndiaDepartment of Computer Science Research Guide Jain University Bangalore IndiaAbstract The test data volume (TDV) increases with increased target compression in scan compression and adds to the test cost. Increased TDV is the result of a dependency across scan flip‐flops (SFFs) that resulted from compression architecture, which is absent in scan mode. The SFFs have uncompressible values logic‐0 and logic‐1 in many or most of the patterns contribute to the TDV. In the proposed new scan compression (NSC) architecture, SFFs are analysed from Automatic Test Pattern Generation (ATPG) patterns generated in a scan mode. The identification of SFFs to be moved out of the compression architecture is carried out based on the NSC. The method includes a ranking of SFFs based on the specified values present in the test patterns. The SFFs having higher specified values are moved out of the compression architecture and placed in the outside scan chain. The NSC is the combination of scan compression and scan mode. This method decides the percentage (%) of SFFs to be moved out of compression architecture and is less than 0.5% of the total SFFs present in the design to achieve a better result. The NSC reduces dependencies across the SFFs present in the test compression architecture. It reduces the TDV and test application time. The results show a significant reduction in the TDV up to 78.14% for the same test coverage.https://doi.org/10.1049/cdt2.12020automatic test pattern generationdata compressionflip‐flopsintegrated circuit testinglogic designlogic testing |
| spellingShingle | Pralhadrao V. Shantagiri Rohit Kapur Chandrasekar Shastry New scan compression approach to reduce the test data volume IET Computers & Digital Techniques automatic test pattern generation data compression flip‐flops integrated circuit testing logic design logic testing |
| title | New scan compression approach to reduce the test data volume |
| title_full | New scan compression approach to reduce the test data volume |
| title_fullStr | New scan compression approach to reduce the test data volume |
| title_full_unstemmed | New scan compression approach to reduce the test data volume |
| title_short | New scan compression approach to reduce the test data volume |
| title_sort | new scan compression approach to reduce the test data volume |
| topic | automatic test pattern generation data compression flip‐flops integrated circuit testing logic design logic testing |
| url | https://doi.org/10.1049/cdt2.12020 |
| work_keys_str_mv | AT pralhadraovshantagiri newscancompressionapproachtoreducethetestdatavolume AT rohitkapur newscancompressionapproachtoreducethetestdatavolume AT chandrasekarshastry newscancompressionapproachtoreducethetestdatavolume |