Joint security and performance improvement in multilevel shared caches
Abstract Multilevel cache architectures are widely used in modern heterogeneous systems for performance improvement. However, satisfying the performance and security requirements at the same time is a challenge for such systems. A simple and efficient timing attack on the shared portions of multilev...
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| Format: | Article |
| Language: | English |
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Wiley
2021-07-01
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| Series: | IET Information Security |
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| Online Access: | https://doi.org/10.1049/ise2.12023 |
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| author | Amin Sarihi Ahmad Patooghy Mahdi Amininasab Mohammad Shokrolah Shirazi Abdel‐Hameed A. Badawy |
| author_facet | Amin Sarihi Ahmad Patooghy Mahdi Amininasab Mohammad Shokrolah Shirazi Abdel‐Hameed A. Badawy |
| author_sort | Amin Sarihi |
| collection | DOAJ |
| description | Abstract Multilevel cache architectures are widely used in modern heterogeneous systems for performance improvement. However, satisfying the performance and security requirements at the same time is a challenge for such systems. A simple and efficient timing attack on the shared portions of multilevel hierarchical caches and its corresponding countermeasure is proposed here. The proposed attack prolongs the execution time of the victim threads by inducing intentional race conditions in shared memory spaces. Then, a thread‐mapping algorithm to detect such race conditions between a group of threads and resolve them as a countermeasure against the attack is proposed. The proposed countermeasure dynamically monitors races on cache blocks and distributes existing and new threads on processing cores to minimize cache contention. Upon detection of a high contention rate that might be either due to an attack or a natural race condition, two mechanisms, namely cache access‐rate reduction and thread migration, will be used by the countermeasure algorithm to resolve the race situation. Evaluations on SPECCPU 2006 benchmark suite show that the proposed algorithm not only protects the system against the introduced attack but also boosts the overall system performance by an average of 46.35% and 55.92% for the worst and average cases, respectively. |
| format | Article |
| id | doaj-art-dd9b39939e054581b35e22845edc4b1f |
| institution | Kabale University |
| issn | 1751-8709 1751-8717 |
| language | English |
| publishDate | 2021-07-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Information Security |
| spelling | doaj-art-dd9b39939e054581b35e22845edc4b1f2025-02-03T01:31:54ZengWileyIET Information Security1751-87091751-87172021-07-0115429730810.1049/ise2.12023Joint security and performance improvement in multilevel shared cachesAmin Sarihi0Ahmad Patooghy1Mahdi Amininasab2Mohammad Shokrolah Shirazi3Abdel‐Hameed A. Badawy4Klipsch School of Electrical and Computer Engineering, New Mexico State University Las Cruces New Mexico USADepartment of Computer Science, University of Central Arkansas Conway Arkansas USAIndependent scholarR.B. Annis School of Engineering, University of Indianapolis Indianapolis Indiana USAKlipsch School of Electrical and Computer Engineering, New Mexico State University Las Cruces New Mexico USAAbstract Multilevel cache architectures are widely used in modern heterogeneous systems for performance improvement. However, satisfying the performance and security requirements at the same time is a challenge for such systems. A simple and efficient timing attack on the shared portions of multilevel hierarchical caches and its corresponding countermeasure is proposed here. The proposed attack prolongs the execution time of the victim threads by inducing intentional race conditions in shared memory spaces. Then, a thread‐mapping algorithm to detect such race conditions between a group of threads and resolve them as a countermeasure against the attack is proposed. The proposed countermeasure dynamically monitors races on cache blocks and distributes existing and new threads on processing cores to minimize cache contention. Upon detection of a high contention rate that might be either due to an attack or a natural race condition, two mechanisms, namely cache access‐rate reduction and thread migration, will be used by the countermeasure algorithm to resolve the race situation. Evaluations on SPECCPU 2006 benchmark suite show that the proposed algorithm not only protects the system against the introduced attack but also boosts the overall system performance by an average of 46.35% and 55.92% for the worst and average cases, respectively.https://doi.org/10.1049/ise2.12023cache storagemultiprocessing systemsresource allocation |
| spellingShingle | Amin Sarihi Ahmad Patooghy Mahdi Amininasab Mohammad Shokrolah Shirazi Abdel‐Hameed A. Badawy Joint security and performance improvement in multilevel shared caches IET Information Security cache storage multiprocessing systems resource allocation |
| title | Joint security and performance improvement in multilevel shared caches |
| title_full | Joint security and performance improvement in multilevel shared caches |
| title_fullStr | Joint security and performance improvement in multilevel shared caches |
| title_full_unstemmed | Joint security and performance improvement in multilevel shared caches |
| title_short | Joint security and performance improvement in multilevel shared caches |
| title_sort | joint security and performance improvement in multilevel shared caches |
| topic | cache storage multiprocessing systems resource allocation |
| url | https://doi.org/10.1049/ise2.12023 |
| work_keys_str_mv | AT aminsarihi jointsecurityandperformanceimprovementinmultilevelsharedcaches AT ahmadpatooghy jointsecurityandperformanceimprovementinmultilevelsharedcaches AT mahdiamininasab jointsecurityandperformanceimprovementinmultilevelsharedcaches AT mohammadshokrolahshirazi jointsecurityandperformanceimprovementinmultilevelsharedcaches AT abdelhameedabadawy jointsecurityandperformanceimprovementinmultilevelsharedcaches |