An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
Reconfigurable logic devices (RLDs) are classified as the fine-grained or coarse-grained type based on their basic logic cell architecture. In general, each architecture has its own advantage. Therefore, it is difficult to achieve a balance between the operation speed and implementation area in vari...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2008-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2008/180216 |
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| author | Motoki Amagasaki Ryoichi Yamaguchi Masahiro Koga Masahiro Iida Toshinori Sueyoshi |
| author_facet | Motoki Amagasaki Ryoichi Yamaguchi Masahiro Koga Masahiro Iida Toshinori Sueyoshi |
| author_sort | Motoki Amagasaki |
| collection | DOAJ |
| description | Reconfigurable logic devices (RLDs) are classified as the fine-grained or coarse-grained type based on their basic logic cell architecture. In general, each architecture has its own advantage. Therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In the present paper, we propose a variable grain logic cell (VGLC) architecture, which consists of a 4-bit ripple carry adder with configuration memory bits and develop a technology mapping tool. The key feature of the VGLC architecture is that the variable granularity is a tradeoff between coarse-grained and fine-grained types required for the implementation arithmetic and random logic, respectively. Finally, we evaluate the proposed logic cell using the newly developed technology mapping tool, which improves
logic depth by 31% and reduces the number of configuration data by 55% on average, as compared to the Virtex-4 logic cell architecture. |
| format | Article |
| id | doaj-art-db8bc320a14d4cc7af17212c13765582 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2008-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-db8bc320a14d4cc7af17212c137655822025-02-03T01:03:29ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092008-01-01200810.1155/2008/180216180216An Embedded Reconfigurable IP Core with Variable Grain Logic Cell ArchitectureMotoki Amagasaki0Ryoichi Yamaguchi1Masahiro Koga2Masahiro Iida3Toshinori Sueyoshi4Graduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Kumamoto 860-8555, JapanGraduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Kumamoto 860-8555, JapanGraduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Kumamoto 860-8555, JapanGraduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Kumamoto 860-8555, JapanGraduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Kumamoto 860-8555, JapanReconfigurable logic devices (RLDs) are classified as the fine-grained or coarse-grained type based on their basic logic cell architecture. In general, each architecture has its own advantage. Therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In the present paper, we propose a variable grain logic cell (VGLC) architecture, which consists of a 4-bit ripple carry adder with configuration memory bits and develop a technology mapping tool. The key feature of the VGLC architecture is that the variable granularity is a tradeoff between coarse-grained and fine-grained types required for the implementation arithmetic and random logic, respectively. Finally, we evaluate the proposed logic cell using the newly developed technology mapping tool, which improves logic depth by 31% and reduces the number of configuration data by 55% on average, as compared to the Virtex-4 logic cell architecture.http://dx.doi.org/10.1155/2008/180216 |
| spellingShingle | Motoki Amagasaki Ryoichi Yamaguchi Masahiro Koga Masahiro Iida Toshinori Sueyoshi An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture International Journal of Reconfigurable Computing |
| title | An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture |
| title_full | An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture |
| title_fullStr | An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture |
| title_full_unstemmed | An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture |
| title_short | An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture |
| title_sort | embedded reconfigurable ip core with variable grain logic cell architecture |
| url | http://dx.doi.org/10.1155/2008/180216 |
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