Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics
In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2019-01-01
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| Series: | Journal of Nanotechnology |
| Online Access: | http://dx.doi.org/10.1155/2019/4935073 |
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