Higher-order HDL: Applied to MLP neural network hardware implementation
In this article, we describe a methodology for the rapid implementation of a hardware architecture using a higher-order approach. This methodology uses a combination of TCL and VHDL for higher-order coding (i.e. code produced by code) and is supported by industry-standard HDL development tools. To e...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
EDP Sciences
2025-01-01
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| Series: | E3S Web of Conferences |
| Online Access: | https://www.e3s-conferences.org/articles/e3sconf/pdf/2025/31/e3sconf_mdoa2025_02004.pdf |
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