Analysis of GAA Junction Less NS FET Towards Analog and RF Applications at 30 nm Regime
This research focuses on a quantum model created using an entirely novel nanosheet FET. The standard model describes the performance of a Gate-all-around (GAA) Junction-less (JL) nanosheet device with a gate dielectric of SiO<sub>2</sub> and HfO<sub>2</sub>, each having a thi...
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| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of Nanotechnology |
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| Online Access: | https://ieeexplore.ieee.org/document/10433722/ |
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| author | Asisa Kumar Panigrahy Sudheer Hanumanthakari Shridhar B. Devamane Shruti Bhargava Choubey M. Prasad D. Somasundaram N. Kumareshan N. Arun Vignesh Gnanasaravanan Subramaniam Durga Prakash M Raghunandan Swain |
| author_facet | Asisa Kumar Panigrahy Sudheer Hanumanthakari Shridhar B. Devamane Shruti Bhargava Choubey M. Prasad D. Somasundaram N. Kumareshan N. Arun Vignesh Gnanasaravanan Subramaniam Durga Prakash M Raghunandan Swain |
| author_sort | Asisa Kumar Panigrahy |
| collection | DOAJ |
| description | This research focuses on a quantum model created using an entirely novel nanosheet FET. The standard model describes the performance of a Gate-all-around (GAA) Junction-less (JL) nanosheet device with a gate dielectric of SiO<sub>2</sub> and HfO<sub>2</sub>, each having a thickness of 1 nm. The performance of both the classical and quantum models of the GAA nanosheet device is evaluated using the visual TCAD tool, which measures the <italic>I<sub>ON</sub></italic>, <italic>I<sub>OFF</sub></italic>, <italic>I<sub>ON</sub>/ I<sub>OFF</sub></italic>, threshold voltage, DIBL, gain parameters (g<sub>m</sub>, g<sub>d</sub>, A<sub>v</sub>), gate capacitance, and cut-off frequency (<italic>f<sub>T</sub></italic>). The device is suited for applications needing rapid switching since it has a low gate capacitance of the order of 10<sup>–18</sup>, according to the simulation results. A transconductance (g<sub>m</sub>) value of 21 µS and an impressive cut-off frequency of 9.03 GHz are displayed during device analysis. A detailed investigation has also been done into the P-type device response for the same device. Finally, the proposed GAA nanosheet device is used in the inverter model. The NSFET-based inverter, although having higher gate capacitance, has the shortest propagation latency. |
| format | Article |
| id | doaj-art-c7a27a7b45314661aa163b68f5786f89 |
| institution | Kabale University |
| issn | 2644-1292 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Nanotechnology |
| spelling | doaj-art-c7a27a7b45314661aa163b68f5786f892025-01-24T00:02:21ZengIEEEIEEE Open Journal of Nanotechnology2644-12922024-01-0151810.1109/OJNANO.2024.336517310433722Analysis of GAA Junction Less NS FET Towards Analog and RF Applications at 30 nm RegimeAsisa Kumar Panigrahy0https://orcid.org/0000-0002-9491-5310Sudheer Hanumanthakari1https://orcid.org/0000-0003-1199-8155Shridhar B. Devamane2https://orcid.org/0000-0002-9979-065XShruti Bhargava Choubey3https://orcid.org/0000-0003-4644-470XM. Prasad4https://orcid.org/0000-0002-2878-9045D. Somasundaram5https://orcid.org/0000-0002-7496-940XN. Kumareshan6https://orcid.org/0000-0002-6853-5891N. Arun Vignesh7https://orcid.org/0000-0002-1026-2958Gnanasaravanan Subramaniam8https://orcid.org/0000-0001-6714-2204Durga Prakash M9https://orcid.org/0000-0001-9143-0628Raghunandan Swain10https://orcid.org/0000-0002-4441-1659Department of ECE, Faculty of Science and Technology (IcfaiTech), ICFAI foundation for Higher Education Hyderabad, Hyderabad, IndiaDepartment of ECE, Faculty of Science and Technology (IcfaiTech), ICFAI foundation for Higher Education Hyderabad, Hyderabad, IndiaDepartment of CSE, Global Academy of Technology, Bangalore, IndiaDepartment of ECE, Sreenidhi Institute of Science and Technology, Hyderabad, IndiaDepartment of ECE, REVA University, Bengaluru, IndiaSchool of Electronics Engineering, VIT, Vellore, IndiaDepartment of ECE, Sri Eshwar College of Engineering, Coimbatore, IndiaDepartment of ECE, GRIET Hyderabad, Hyderabad, IndiaDepartment of Biomedical Engineering, Karunya Institute of Technology and Sciences, Coimbatore, IndiaDepartment of Electronics and Communication Engineering, School of Engineering and Sciences, SRM University-AP, Amaravati, IndiaDepartment of E & TC, Parala Maharaja Engineering College, Berhampur, IndiaThis research focuses on a quantum model created using an entirely novel nanosheet FET. The standard model describes the performance of a Gate-all-around (GAA) Junction-less (JL) nanosheet device with a gate dielectric of SiO<sub>2</sub> and HfO<sub>2</sub>, each having a thickness of 1 nm. The performance of both the classical and quantum models of the GAA nanosheet device is evaluated using the visual TCAD tool, which measures the <italic>I<sub>ON</sub></italic>, <italic>I<sub>OFF</sub></italic>, <italic>I<sub>ON</sub>/ I<sub>OFF</sub></italic>, threshold voltage, DIBL, gain parameters (g<sub>m</sub>, g<sub>d</sub>, A<sub>v</sub>), gate capacitance, and cut-off frequency (<italic>f<sub>T</sub></italic>). The device is suited for applications needing rapid switching since it has a low gate capacitance of the order of 10<sup>–18</sup>, according to the simulation results. A transconductance (g<sub>m</sub>) value of 21 µS and an impressive cut-off frequency of 9.03 GHz are displayed during device analysis. A detailed investigation has also been done into the P-type device response for the same device. Finally, the proposed GAA nanosheet device is used in the inverter model. The NSFET-based inverter, although having higher gate capacitance, has the shortest propagation latency.https://ieeexplore.ieee.org/document/10433722/CMOS inverterdielectricshigh-kgate-all-aroundquantum effectstransient analysis |
| spellingShingle | Asisa Kumar Panigrahy Sudheer Hanumanthakari Shridhar B. Devamane Shruti Bhargava Choubey M. Prasad D. Somasundaram N. Kumareshan N. Arun Vignesh Gnanasaravanan Subramaniam Durga Prakash M Raghunandan Swain Analysis of GAA Junction Less NS FET Towards Analog and RF Applications at 30 nm Regime IEEE Open Journal of Nanotechnology CMOS inverter dielectrics high-k gate-all-around quantum effects transient analysis |
| title | Analysis of GAA Junction Less NS FET Towards Analog and RF Applications at 30 nm Regime |
| title_full | Analysis of GAA Junction Less NS FET Towards Analog and RF Applications at 30 nm Regime |
| title_fullStr | Analysis of GAA Junction Less NS FET Towards Analog and RF Applications at 30 nm Regime |
| title_full_unstemmed | Analysis of GAA Junction Less NS FET Towards Analog and RF Applications at 30 nm Regime |
| title_short | Analysis of GAA Junction Less NS FET Towards Analog and RF Applications at 30 nm Regime |
| title_sort | analysis of gaa junction less ns fet towards analog and rf applications at 30 nm regime |
| topic | CMOS inverter dielectrics high-k gate-all-around quantum effects transient analysis |
| url | https://ieeexplore.ieee.org/document/10433722/ |
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