FPGA‐based implementation of floating point processing element for the design of efficient FIR filters
Abstract Numerous applications based on very large scale intergration (VLSI) architecture suffer from large size components that lead to an error in the design of the filter during the stages of floating point arithmetic. Hence, it is necessary to change the architectural model that increases the de...
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Wiley
2021-07-01
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| Series: | IET Computers & Digital Techniques |
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| Online Access: | https://doi.org/10.1049/cdt2.12010 |
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| author | Tintu Mary John Shanty Chacko |
| author_facet | Tintu Mary John Shanty Chacko |
| author_sort | Tintu Mary John |
| collection | DOAJ |
| description | Abstract Numerous applications based on very large scale intergration (VLSI) architecture suffer from large size components that lead to an error in the design of the filter during the stages of floating point arithmetic. Hence, it is necessary to change the architectural model that increases the design complexity and the time delay effect. The issue encountered in the VLSI architectures for finite impulse response (FIR) filter is the increased number of components, especially delay elements. For the VLSI architecture reconfigured with reduced register usage, this article provides the floating point processing element (FPPE) implementation with Cross‐Folded Shifting. The proposed FIR filter system reduces the number of components in the circuit which increases the complexity and high delay rate in the logical operation. The system has a comparatively reduced delay rate and power consumption. Hence, an efficient fast architecture based on the FPPE method is developed in this paper. |
| format | Article |
| id | doaj-art-ba5ae9dad65b491eadf91c7597d797da |
| institution | Kabale University |
| issn | 1751-8601 1751-861X |
| language | English |
| publishDate | 2021-07-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj-art-ba5ae9dad65b491eadf91c7597d797da2025-02-03T01:29:41ZengWileyIET Computers & Digital Techniques1751-86011751-861X2021-07-0115429630110.1049/cdt2.12010FPGA‐based implementation of floating point processing element for the design of efficient FIR filtersTintu Mary John0Shanty Chacko1School of Electrical Sciences Electronics & Communication Engineering Karunya Institute of Technology & Sciences Coimbatore IndiaSchool of Electrical Sciences Electrical & Electronics Engineering Karunya Institute of Technology & Sciences Coimbatore IndiaAbstract Numerous applications based on very large scale intergration (VLSI) architecture suffer from large size components that lead to an error in the design of the filter during the stages of floating point arithmetic. Hence, it is necessary to change the architectural model that increases the design complexity and the time delay effect. The issue encountered in the VLSI architectures for finite impulse response (FIR) filter is the increased number of components, especially delay elements. For the VLSI architecture reconfigured with reduced register usage, this article provides the floating point processing element (FPPE) implementation with Cross‐Folded Shifting. The proposed FIR filter system reduces the number of components in the circuit which increases the complexity and high delay rate in the logical operation. The system has a comparatively reduced delay rate and power consumption. Hence, an efficient fast architecture based on the FPPE method is developed in this paper.https://doi.org/10.1049/cdt2.12010delaysfield programmable gate arraysFIR filtersfloating point arithmeticVLSI |
| spellingShingle | Tintu Mary John Shanty Chacko FPGA‐based implementation of floating point processing element for the design of efficient FIR filters IET Computers & Digital Techniques delays field programmable gate arrays FIR filters floating point arithmetic VLSI |
| title | FPGA‐based implementation of floating point processing element for the design of efficient FIR filters |
| title_full | FPGA‐based implementation of floating point processing element for the design of efficient FIR filters |
| title_fullStr | FPGA‐based implementation of floating point processing element for the design of efficient FIR filters |
| title_full_unstemmed | FPGA‐based implementation of floating point processing element for the design of efficient FIR filters |
| title_short | FPGA‐based implementation of floating point processing element for the design of efficient FIR filters |
| title_sort | fpga based implementation of floating point processing element for the design of efficient fir filters |
| topic | delays field programmable gate arrays FIR filters floating point arithmetic VLSI |
| url | https://doi.org/10.1049/cdt2.12010 |
| work_keys_str_mv | AT tintumaryjohn fpgabasedimplementationoffloatingpointprocessingelementforthedesignofefficientfirfilters AT shantychacko fpgabasedimplementationoffloatingpointprocessingelementforthedesignofefficientfirfilters |