Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET
Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel...
Saved in:
Main Authors: | Satyam Shukla, Sandeep Singh Gill, Navneet Kaur, H. S. Jatana, Varun Nehru |
---|---|
Format: | Article |
Language: | English |
Published: |
Wiley
2017-01-01
|
Series: | Active and Passive Electronic Components |
Online Access: | http://dx.doi.org/10.1155/2017/5947819 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Efficient Implementation of Mahalanobis Distance on Ferroelectric FinFET Crossbar for Outlier Detection
by: Musaib Rafiq, et al.
Published: (2024-01-01) -
SpaceCAM: A 16 nm FinFET Low-Power Soft-Error Tolerant TCAM Design for Space Communication Applications
by: Itay Merlin, et al.
Published: (2025-01-01) -
BDD-Based Topology Optimization for Low-Power DTIG FinFET Circuits
by: Haiyan Ni, et al.
Published: (2019-01-01) -
Comprehensive analysis of In0.53Ga0.47As SOI-FinFET for enhanced RF/wireless performance
by: Priyanka Agrwal, et al.
Published: (2025-02-01) -
Process-Dependent Evolution of Channel Stress and Stress-Induced Mobility Gain in FinFET, Normal GAAFET, and Si/SiGe Hybrid Channel GAAFET
by: Chiang Zhu, et al.
Published: (2025-01-01)