FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture
The higher computational complexity of an elliptic curve scalar point multiplication operation limits its implementation on general purpose processors. Dedicated hardware architectures are essential to reduce the computational time, which results in a substantial increase in the performance of assoc...
Saved in:
| Main Authors: | Khalid Javeed, Xiaojun Wang |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2016-01-01
|
| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2016/6371403 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Design and implementation of high-speed scalar multiplier for multi-elliptic curve
by: Bin YU, et al.
Published: (2020-12-01) -
HIGH-SPEED MULTIPLIER DESIGN BASED ON AN OPTIMIZED PARALLEL PREFIX TREE ARCHITECTURE
by: D. V. N. Bharathi, et al.
Published: (2025-06-01) -
Algorithm of NAF scalar multiplication on ECC against SPA
by: Min WANG, et al.
Published: (2012-09-01) -
An Improved GN-AK Protocol Using Double-Base Scalar Multiplication and Point Halving over Elliptic Curves
by: Nicolae Constantinescu, et al.
Published: (2025-07-01) -
Floating Point Multiple-Precision Fused Multiply Add Architecture for Deep Learning Computation on Artix 7 FPGA Board
by: VINOTHENI, M. S., et al.
Published: (2024-11-01)