Low power‐delay‐product dynamic CMOS circuit design techniques
Two low power‐delay‐product (PDP) dynamic CMOS circuit design techniques are proposed. The techniques can simply modify existing dynamic CMOS designs to improve dynamic circuit delay and PDP. Conventional benchmark circuits and the modified circuits using the proposed techniques are implemented in 9...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2017-03-01
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| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/el.2016.4173 |
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| Summary: | Two low power‐delay‐product (PDP) dynamic CMOS circuit design techniques are proposed. The techniques can simply modify existing dynamic CMOS designs to improve dynamic circuit delay and PDP. Conventional benchmark circuits and the modified circuits using the proposed techniques are implemented in 90 nm CMOS technology with a 1.2 V power supply. Simulation results indicate that the proposed techniques can improve circuit PDP by 19.2 and 61.9% in two non‐inverted dynamic benchmarks, respectively, and 6.2 and 33.72% in two inverted dynamic benchmarks, respectively. |
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| ISSN: | 0013-5194 1350-911X |