IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions
Abstract A secure processor requires that no secret, undocumented instructions be executed. Unfortunately, as today's processor design and supply chain are increasingly complex, undocumented instructions that can execute some specific functions can still be secretly introduced into the processo...
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| Format: | Article |
| Language: | English |
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Wiley
2022-07-01
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| Series: | IET Information Security |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/ise2.12059 |
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| _version_ | 1832558679130374144 |
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| author | Yuze Wang Peng Liu Yingtao Jiang |
| author_facet | Yuze Wang Peng Liu Yingtao Jiang |
| author_sort | Yuze Wang |
| collection | DOAJ |
| description | Abstract A secure processor requires that no secret, undocumented instructions be executed. Unfortunately, as today's processor design and supply chain are increasingly complex, undocumented instructions that can execute some specific functions can still be secretly introduced into the processor system as flaws or vulnerabilities. To address this problem that may cause potentially serious security breaches, the instruction set architecture (ISA) monitor and secure cache (IMSC) is proposed. As a lightweight solution, IMSC employs an ISA monitor to discover and correct any potential threats imposed by undocumented instructions, and it relies on a secure cache to ensure the credibility of the system. The authors’ case studies have confirmed that IMSC can effectively protect a processor system from being exploited by undocumented instructions and thus provide a trustworthy computing environment, all at low hardware and run‐time costs. |
| format | Article |
| id | doaj-art-ae25f02d1b3746718f1bb708c0415d6a |
| institution | Kabale University |
| issn | 1751-8709 1751-8717 |
| language | English |
| publishDate | 2022-07-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Information Security |
| spelling | doaj-art-ae25f02d1b3746718f1bb708c0415d6a2025-02-03T01:31:54ZengWileyIET Information Security1751-87091751-87172022-07-0116431431910.1049/ise2.12059IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructionsYuze Wang0Peng Liu1Yingtao Jiang2College of Information Science and Electronic Engineering Zhejiang University Hangzhou ChinaCollege of Information Science and Electronic Engineering Zhejiang University Hangzhou ChinaDepartment of Electrical and Computer Engineering University of Nevada Las Vegas Las Vegas Nevada USAAbstract A secure processor requires that no secret, undocumented instructions be executed. Unfortunately, as today's processor design and supply chain are increasingly complex, undocumented instructions that can execute some specific functions can still be secretly introduced into the processor system as flaws or vulnerabilities. To address this problem that may cause potentially serious security breaches, the instruction set architecture (ISA) monitor and secure cache (IMSC) is proposed. As a lightweight solution, IMSC employs an ISA monitor to discover and correct any potential threats imposed by undocumented instructions, and it relies on a secure cache to ensure the credibility of the system. The authors’ case studies have confirmed that IMSC can effectively protect a processor system from being exploited by undocumented instructions and thus provide a trustworthy computing environment, all at low hardware and run‐time costs.https://doi.org/10.1049/ise2.12059instruction setstrusted computing |
| spellingShingle | Yuze Wang Peng Liu Yingtao Jiang IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions IET Information Security instruction sets trusted computing |
| title | IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions |
| title_full | IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions |
| title_fullStr | IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions |
| title_full_unstemmed | IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions |
| title_short | IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions |
| title_sort | imsc instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions |
| topic | instruction sets trusted computing |
| url | https://doi.org/10.1049/ise2.12059 |
| work_keys_str_mv | AT yuzewang imscinstructionsetarchitecturemonitorandsecurecacheforprotectingprocessorsystemsfromundocumentedinstructions AT pengliu imscinstructionsetarchitecturemonitorandsecurecacheforprotectingprocessorsystemsfromundocumentedinstructions AT yingtaojiang imscinstructionsetarchitecturemonitorandsecurecacheforprotectingprocessorsystemsfromundocumentedinstructions |