Design and Implementation of a 16-bit Multi-Mode Delta-Sigma Digital-to-Analog Converter with Time-Interleaved Structure, Multi-Channel, and Compensation of Non-Idealities Based on FPGA

Design and Implementation of a 16-bit Multi-Mode Delta-Sigma Digital-to-Analog Converter with Time-Interleaved Structure, Multi-Channel, and Compensation of Non-Idealities Based on FPGA

<p>In this research, a 16-bit multi-mode second-order Delta-Sigma Modulator-Digital-to-Analog Converter (DSM-DAC) with a time-interleaved (TI) structure operating at a center frequency of 4 GHz and a bandwidth of 20 MHz has been implemented using VHDL on an FPGA platform. The proposed architec...

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Bibliographic Details
Main Authors: Abolfazl Roshanpanah, Pooya Torkzadeh, Khosrow Hajsadeghi, Massoud Dousti
Format: Article
Language:fas
Published: Islamic Azad University Bushehr Branch 2025-01-01
Series:مهندسی مخابرات جنوب
Subjects:
delta-sigma modulator
duty-cycle-error
error-feedback
fpga
mismatch
time-interleaved
Online Access:https://sanad.iau.ir/journal/jce/Article/1105014
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