Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field

Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field

Abstract The performance of any elliptic curve cryptography hardware accelerator significantly relies on the efficiency of the underlying point multiplication (PM) architecture. This article presents a hardware implementation of field-programmable gate array (FPGA) based modular arithmetic, group op...

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Bibliographic Details
Main Authors: Md Rownak Hossain, Md Sazedur Rahman, Kh Shahriya Zaman, Walid El Fezzani, Mohammad Arif Sobhan Bhuiyan, Chia Chao Kang, Teh Jia Yew, Mahdi H. Miraz
Format: Article
Language:English
Published: Nature Portfolio 2025-04-01
Series:Scientific Reports
Subjects:
ECC hardware accelerator
Modular multiplication
Unified point operation
Point multiplication
Twisted Edward curve
Field programmable gate array (FPGA)
Online Access:https://doi.org/10.1038/s41598-025-99100-x
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https://doi.org/10.1038/s41598-025-99100-x

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