FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study
Reconfigurable computers usually provide a limited number of different memory resources, such as host memory, external memory, and on-chip memory with different capacities and communication characteristics. A key challenge for achieving high-performance with reconfigurable accelerators is the effici...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2011-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2011/760954 |
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| _version_ | 1832550368854147072 |
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| author | Tobias Schumacher Tim Süß Christian Plessl Marco Platzner |
| author_facet | Tobias Schumacher Tim Süß Christian Plessl Marco Platzner |
| author_sort | Tobias Schumacher |
| collection | DOAJ |
| description | Reconfigurable computers usually provide a limited
number of different memory resources, such as host
memory, external memory, and on-chip memory with different
capacities and communication characteristics. A key
challenge for achieving high-performance with reconfigurable
accelerators is the efficient utilization of the available memory
resources. A detailed knowledge of the memories' parameters
is key for generating an optimized communication layout. In this paper, we discuss a benchmarking environment
for generating such a characterization. The environment is
built on IMORC, our architectural template and on-chip
network for creating reconfigurable accelerators. We provide
a characterization of the memory resources available on the
XtremeData XD1000 reconfigurable computer. Based on this
data, we present as a case study the implementation of a 3D
image compositing accelerator that is able to double the frame rate
of a parallel renderer. |
| format | Article |
| id | doaj-art-a853bada28b748c29a2374cfcf9f79b4 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2011-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-a853bada28b748c29a2374cfcf9f79b42025-02-03T06:07:02ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092011-01-01201110.1155/2011/760954760954FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case StudyTobias Schumacher0Tim Süß1Christian Plessl2Marco Platzner3Paderborn Center for Parallel Computing, University of Paderborn, 33098 Paderborn, GermanyPaderborn Center for Parallel Computing, University of Paderborn, 33098 Paderborn, GermanyPaderborn Center for Parallel Computing, University of Paderborn, 33098 Paderborn, GermanyPaderborn Center for Parallel Computing, University of Paderborn, 33098 Paderborn, GermanyReconfigurable computers usually provide a limited number of different memory resources, such as host memory, external memory, and on-chip memory with different capacities and communication characteristics. A key challenge for achieving high-performance with reconfigurable accelerators is the efficient utilization of the available memory resources. A detailed knowledge of the memories' parameters is key for generating an optimized communication layout. In this paper, we discuss a benchmarking environment for generating such a characterization. The environment is built on IMORC, our architectural template and on-chip network for creating reconfigurable accelerators. We provide a characterization of the memory resources available on the XtremeData XD1000 reconfigurable computer. Based on this data, we present as a case study the implementation of a 3D image compositing accelerator that is able to double the frame rate of a parallel renderer.http://dx.doi.org/10.1155/2011/760954 |
| spellingShingle | Tobias Schumacher Tim Süß Christian Plessl Marco Platzner FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study International Journal of Reconfigurable Computing |
| title | FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study |
| title_full | FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study |
| title_fullStr | FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study |
| title_full_unstemmed | FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study |
| title_short | FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study |
| title_sort | fpga acceleration of communication bound streaming applications architecture modeling and a 3d image compositing case study |
| url | http://dx.doi.org/10.1155/2011/760954 |
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