A 500MS/s 14-bit Pipelined ADC With Startup Protection Circuit in 40 nm CMOS
This paper presents a 500 MS/s 14-bit pipelined analog-to-digital converter (ADC) implemented in a 40 nm CMOS process. During power-up, the system is initially unstable, and the terminal voltage of certain transistors may exceed their specified breakdown voltage, putting them at risk of damage. To a...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10915601/ |
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