PAGR: Accelerating Global Routing for VLSI Design Flow

PAGR: Accelerating Global Routing for VLSI Design Flow

In this paper, we present PAGR (Python Alpha Global Routing) – a solution to the global routing problem in physical synthesis based on data from the ISPD 2024 contest. Our solution constructs a weighted graph and builds a Steiner tree. To accelerate the Steiner tree search, we propose a t...

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Bibliographic Details
Main Authors: Roman A. Solovyev, Ilya A. Mkrtchan, Dmitry V. Telpukhov, Ilya I. Shafeev, Aleksandr Y. Romanov, Yevgeniy V. Stolbikov, Alexander L. Stempkovsky
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
Subjects:
Design flow
global routing
ISPD contest
matrix reduction
Steiner tree
VLSI
Online Access:https://ieeexplore.ieee.org/document/10829948/
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