Fail-Safe Logic Design Strategies Within Modern FPGA Architectures

Fail-Safe Logic Design Strategies Within Modern FPGA Architectures

Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the...

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Bibliographic Details
Main Authors: Priya A. Bhakta, Jim Plusquellic, Andrew Suchanek, Tom J. Mannos
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
Subjects:
DEFCON
duplication-with-comparison
fail-safe
fault injection attacks
single-event-upsets
fault tolerance
Online Access:https://ieeexplore.ieee.org/document/10810411/
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https://ieeexplore.ieee.org/document/10810411/

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