Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization
Abstract This paper proposes an efficient high‐order finite impulse response (FIR) filter structure for field programmable gate array (FPGA)‐based applications with simultaneous digital signal processing (DSP) and look‐up‐table (LUT) reduced utilization. The real‐time updating of the filter coeffici...
Saved in:
| Main Authors: | , , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2021-08-01
|
| Series: | IET Circuits, Devices and Systems |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cds2.12043 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832559637636841472 |
|---|---|
| author | Mountassar Maamoun Adnane Hassani Samir Dahmani Hocine Ait Saadi Ghania Zerari Noureddine Chabini Rachid Beguenane |
| author_facet | Mountassar Maamoun Adnane Hassani Samir Dahmani Hocine Ait Saadi Ghania Zerari Noureddine Chabini Rachid Beguenane |
| author_sort | Mountassar Maamoun |
| collection | DOAJ |
| description | Abstract This paper proposes an efficient high‐order finite impulse response (FIR) filter structure for field programmable gate array (FPGA)‐based applications with simultaneous digital signal processing (DSP) and look‐up‐table (LUT) reduced utilization. The real‐time updating of the filter coefficients is also put into perspective. In order to perform these objectives, both the speed and the structure of FPGA are efficiently exploited. The gap between the required input sampling frequency and the FPGA allowed maximum frequency is managed to achieve additional computing sequences. Furthermore, the special structures of the FPGA Look‐up‐table Shift‐Register (LUT‐SR) and their internal connections are fully employed for pipelining and selecting the input samples. The FPGA Block RAMs (BRAMs) are employed for handling the reconfigurable filter coefficients, and the FPGA DSP slices are associated for computing the output data of the BRAMs and the multiplexers. To synchronize the BRAM unit addressing with the LUT multiplexer selection, a single unit is used for simultaneous control. The obtained results show that the proposed reconfigurable 16‐tap FIR filter offers reductions of 79.3% and 74.4% of slice utilization over the hybrid variable size partitioning (VP‐Hybrid) based structure and the Radix‐2r based structure, respectively when implemented on a Xilinx Spartan‐6 XC6SLX45 FPGA. Moreover, an improvement of efficiency is achieved compared to all reputed FPGA‐based architectures. |
| format | Article |
| id | doaj-art-96244c7e0826458aa29054659b76369f |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2021-08-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-96244c7e0826458aa29054659b76369f2025-02-03T01:29:39ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982021-08-0115547548410.1049/cds2.12043Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilizationMountassar Maamoun0Adnane Hassani1Samir Dahmani2Hocine Ait Saadi3Ghania Zerari4Noureddine Chabini5Rachid Beguenane6LATSI Laboratory Department of Electronics University of Blida Blida AlgeriaLSIC Laboratory Department of Physics ENS de Kouba Vieux‐Kouba Algiers AlgeriaLATSI Laboratory Department of Electronics University of Blida Blida AlgeriaLATSI Laboratory Department of Electronics University of Blida Blida AlgeriaLATSI Laboratory Department of Electronics University of Blida Blida AlgeriaDepartment of Electrical and Computer Engineering Royal Military College of Canada Kingston CanadaDepartment of Electrical and Computer Engineering Royal Military College of Canada Kingston CanadaAbstract This paper proposes an efficient high‐order finite impulse response (FIR) filter structure for field programmable gate array (FPGA)‐based applications with simultaneous digital signal processing (DSP) and look‐up‐table (LUT) reduced utilization. The real‐time updating of the filter coefficients is also put into perspective. In order to perform these objectives, both the speed and the structure of FPGA are efficiently exploited. The gap between the required input sampling frequency and the FPGA allowed maximum frequency is managed to achieve additional computing sequences. Furthermore, the special structures of the FPGA Look‐up‐table Shift‐Register (LUT‐SR) and their internal connections are fully employed for pipelining and selecting the input samples. The FPGA Block RAMs (BRAMs) are employed for handling the reconfigurable filter coefficients, and the FPGA DSP slices are associated for computing the output data of the BRAMs and the multiplexers. To synchronize the BRAM unit addressing with the LUT multiplexer selection, a single unit is used for simultaneous control. The obtained results show that the proposed reconfigurable 16‐tap FIR filter offers reductions of 79.3% and 74.4% of slice utilization over the hybrid variable size partitioning (VP‐Hybrid) based structure and the Radix‐2r based structure, respectively when implemented on a Xilinx Spartan‐6 XC6SLX45 FPGA. Moreover, an improvement of efficiency is achieved compared to all reputed FPGA‐based architectures.https://doi.org/10.1049/cds2.12043digital signal processing chipsfield programmable gate arraysFIR filtersrandom‐access storagetable lookup |
| spellingShingle | Mountassar Maamoun Adnane Hassani Samir Dahmani Hocine Ait Saadi Ghania Zerari Noureddine Chabini Rachid Beguenane Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization IET Circuits, Devices and Systems digital signal processing chips field programmable gate arrays FIR filters random‐access storage table lookup |
| title | Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization |
| title_full | Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization |
| title_fullStr | Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization |
| title_full_unstemmed | Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization |
| title_short | Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization |
| title_sort | efficient fpga based architecture for high order fir filtering using simultaneous dsp and lut reduced utilization |
| topic | digital signal processing chips field programmable gate arrays FIR filters random‐access storage table lookup |
| url | https://doi.org/10.1049/cds2.12043 |
| work_keys_str_mv | AT mountassarmaamoun efficientfpgabasedarchitectureforhighorderfirfilteringusingsimultaneousdspandlutreducedutilization AT adnanehassani efficientfpgabasedarchitectureforhighorderfirfilteringusingsimultaneousdspandlutreducedutilization AT samirdahmani efficientfpgabasedarchitectureforhighorderfirfilteringusingsimultaneousdspandlutreducedutilization AT hocineaitsaadi efficientfpgabasedarchitectureforhighorderfirfilteringusingsimultaneousdspandlutreducedutilization AT ghaniazerari efficientfpgabasedarchitectureforhighorderfirfilteringusingsimultaneousdspandlutreducedutilization AT noureddinechabini efficientfpgabasedarchitectureforhighorderfirfilteringusingsimultaneousdspandlutreducedutilization AT rachidbeguenane efficientfpgabasedarchitectureforhighorderfirfilteringusingsimultaneousdspandlutreducedutilization |