Power‐jitter trade‐off analysis in digital‐to‐time converters
Digital‐to‐time converters are one of the main building blocks in time‐domain signal processing. The jitter‐power product is analysed and shown to scale up linearly as the full‐scale delay range in current‐mode logic implementations, and quadratically in CMOS logic. It is also shown that CMOS conver...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2017-03-01
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| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/el.2016.4577 |
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| Summary: | Digital‐to‐time converters are one of the main building blocks in time‐domain signal processing. The jitter‐power product is analysed and shown to scale up linearly as the full‐scale delay range in current‐mode logic implementations, and quadratically in CMOS logic. It is also shown that CMOS converters outperforms current‐mode ones only when their output range is lower than about 1.4 times the clock period. |
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| ISSN: | 0013-5194 1350-911X |