High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects
Currently, we are living in a data-centric era as the need for large amounts of data has dramatically increased due to the widespread adoption of artificial intelligence (AI) in a variety of technology domains. In the current computing architecture, the memory input and output (I/O) bandwidth is bec...
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10677348/ |
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| author | Joo-Hyung Chae |
| author_facet | Joo-Hyung Chae |
| author_sort | Joo-Hyung Chae |
| collection | DOAJ |
| description | Currently, we are living in a data-centric era as the need for large amounts of data has dramatically increased due to the widespread adoption of artificial intelligence (AI) in a variety of technology domains. In the current computing architecture, the memory input and output (I/O) bandwidth is becoming a bottleneck for improving computing performance; therefore, high-bandwidth memory interfaces are essential. In addition, the high power consumption of data centers to edge AI devices will lead to power shortages and climate crises in the near future; therefore, energy-efficient techniques for memory interfaces are also important. This article presents contemporary approaches to improve I/O bandwidth, such as increasing the I/O pin count and data rate/pin, and to save energy in memory interfaces. However, there are still some design challenges that require further improvements. Therefore, various design challenges and problems to be solved are discussed, and future perspectives, including chiplet and die-to-die interfaces, are presented. Based on various research and development efforts to overcome the current limitations, the technological paradigm shift and related industries are expected to advance to the next level. |
| format | Article |
| id | doaj-art-81f4c762a39f40818791e191a76e90ce |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-81f4c762a39f40818791e191a76e90ce2025-01-25T00:03:10ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-01425226410.1109/OJSSCS.2024.345890010677348High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future ProspectsJoo-Hyung Chae0https://orcid.org/0000-0001-6354-5612Department of Electronics and Communications Engineering, Kwangwoon University, Seoul, South KoreaCurrently, we are living in a data-centric era as the need for large amounts of data has dramatically increased due to the widespread adoption of artificial intelligence (AI) in a variety of technology domains. In the current computing architecture, the memory input and output (I/O) bandwidth is becoming a bottleneck for improving computing performance; therefore, high-bandwidth memory interfaces are essential. In addition, the high power consumption of data centers to edge AI devices will lead to power shortages and climate crises in the near future; therefore, energy-efficient techniques for memory interfaces are also important. This article presents contemporary approaches to improve I/O bandwidth, such as increasing the I/O pin count and data rate/pin, and to save energy in memory interfaces. However, there are still some design challenges that require further improvements. Therefore, various design challenges and problems to be solved are discussed, and future perspectives, including chiplet and die-to-die interfaces, are presented. Based on various research and development efforts to overcome the current limitations, the technological paradigm shift and related industries are expected to advance to the next level.https://ieeexplore.ieee.org/document/10677348/Artificial intelligence (AI)dynamic random access memory (DRAM)energy efficiencyhigh bandwidthmemory interface |
| spellingShingle | Joo-Hyung Chae High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects IEEE Open Journal of the Solid-State Circuits Society Artificial intelligence (AI) dynamic random access memory (DRAM) energy efficiency high bandwidth memory interface |
| title | High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects |
| title_full | High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects |
| title_fullStr | High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects |
| title_full_unstemmed | High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects |
| title_short | High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects |
| title_sort | high bandwidth and energy efficient memory interfaces for the data centric era recent advances design challenges and future prospects |
| topic | Artificial intelligence (AI) dynamic random access memory (DRAM) energy efficiency high bandwidth memory interface |
| url | https://ieeexplore.ieee.org/document/10677348/ |
| work_keys_str_mv | AT joohyungchae highbandwidthandenergyefficientmemoryinterfacesforthedatacentricerarecentadvancesdesignchallengesandfutureprospects |