TCAD Simulation Study of Cylindrical Vertical Double-Surrounding-Gate a-InGaZnO FETs and Geometric Parameter Optimization
Threshold control of amorphous In-Ga-Zn-O field-effect transistor (a-IGZO FET) is generally a critical issue through material composition adjustment. Instead, this work reports a cylindrical vertical double-surrounding-gate (DSG) a-IGZO FET, featuring flexibility of threshold modulation, by the 3-D...
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2025-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10836807/ |
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| author | Yue Zhao Lihua Xu Chuanke Chen Xufan Li Kexin Shang Di Geng Lingfei Wang Ling Li |
| author_facet | Yue Zhao Lihua Xu Chuanke Chen Xufan Li Kexin Shang Di Geng Lingfei Wang Ling Li |
| author_sort | Yue Zhao |
| collection | DOAJ |
| description | Threshold control of amorphous In-Ga-Zn-O field-effect transistor (a-IGZO FET) is generally a critical issue through material composition adjustment. Instead, this work reports a cylindrical vertical double-surrounding-gate (DSG) a-IGZO FET, featuring flexibility of threshold modulation, by the 3-D technology computer-aided design (TCAD) simulation. Firstly, physics-based parameters are calibrated to single-gated vertical transistor experiments. Thereafter, the performance is simulated by sweeping inner gate (G1) bias voltages under the various outer gate (G2) voltages, indicating the ability of threshold modulation. Length-scaling and position-variation of <inline-formula> <tex-math notation="LaTeX">$G_{2}$ </tex-math></inline-formula> significantly impact the transistor performance metrics. For in-depth understanding of dimensional dependence, the surface potential of the channel and the electric field distribution near electrode are systematically investigated for an ultra-thin outer gate electrode, via considering spatial and geometric effects. These results will boost a design technology co-optimization flow of the future DSG-a-IGZO-FET-based extremely large-scale and high-density M3D memory. |
| format | Article |
| id | doaj-art-6ff06bfbe5724764b625821b33b87fc9 |
| institution | Kabale University |
| issn | 2168-6734 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-6ff06bfbe5724764b625821b33b87fc92025-01-28T00:00:34ZengIEEEIEEE Journal of the Electron Devices Society2168-67342025-01-0113667210.1109/JEDS.2025.352807310836807TCAD Simulation Study of Cylindrical Vertical Double-Surrounding-Gate a-InGaZnO FETs and Geometric Parameter OptimizationYue Zhao0https://orcid.org/0009-0000-7648-429XLihua Xu1https://orcid.org/0000-0003-2425-0170Chuanke Chen2https://orcid.org/0009-0001-0477-2927Xufan Li3Kexin Shang4https://orcid.org/0009-0002-3688-1869Di Geng5https://orcid.org/0000-0002-5653-6811Lingfei Wang6https://orcid.org/0000-0003-3579-8406Ling Li7https://orcid.org/0000-0002-7622-8752State Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaState Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaState Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaState Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaState Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaState Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaState Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaState Key Laboratory of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics, Chinese Academy of Sciences, Beijing, ChinaThreshold control of amorphous In-Ga-Zn-O field-effect transistor (a-IGZO FET) is generally a critical issue through material composition adjustment. Instead, this work reports a cylindrical vertical double-surrounding-gate (DSG) a-IGZO FET, featuring flexibility of threshold modulation, by the 3-D technology computer-aided design (TCAD) simulation. Firstly, physics-based parameters are calibrated to single-gated vertical transistor experiments. Thereafter, the performance is simulated by sweeping inner gate (G1) bias voltages under the various outer gate (G2) voltages, indicating the ability of threshold modulation. Length-scaling and position-variation of <inline-formula> <tex-math notation="LaTeX">$G_{2}$ </tex-math></inline-formula> significantly impact the transistor performance metrics. For in-depth understanding of dimensional dependence, the surface potential of the channel and the electric field distribution near electrode are systematically investigated for an ultra-thin outer gate electrode, via considering spatial and geometric effects. These results will boost a design technology co-optimization flow of the future DSG-a-IGZO-FET-based extremely large-scale and high-density M3D memory.https://ieeexplore.ieee.org/document/10836807/Vertical transistordouble-surrounding-gateTCADa-IGZOgate lengthgate position |
| spellingShingle | Yue Zhao Lihua Xu Chuanke Chen Xufan Li Kexin Shang Di Geng Lingfei Wang Ling Li TCAD Simulation Study of Cylindrical Vertical Double-Surrounding-Gate a-InGaZnO FETs and Geometric Parameter Optimization IEEE Journal of the Electron Devices Society Vertical transistor double-surrounding-gate TCAD a-IGZO gate length gate position |
| title | TCAD Simulation Study of Cylindrical Vertical Double-Surrounding-Gate a-InGaZnO FETs and Geometric Parameter Optimization |
| title_full | TCAD Simulation Study of Cylindrical Vertical Double-Surrounding-Gate a-InGaZnO FETs and Geometric Parameter Optimization |
| title_fullStr | TCAD Simulation Study of Cylindrical Vertical Double-Surrounding-Gate a-InGaZnO FETs and Geometric Parameter Optimization |
| title_full_unstemmed | TCAD Simulation Study of Cylindrical Vertical Double-Surrounding-Gate a-InGaZnO FETs and Geometric Parameter Optimization |
| title_short | TCAD Simulation Study of Cylindrical Vertical Double-Surrounding-Gate a-InGaZnO FETs and Geometric Parameter Optimization |
| title_sort | tcad simulation study of cylindrical vertical double surrounding gate a ingazno fets and geometric parameter optimization |
| topic | Vertical transistor double-surrounding-gate TCAD a-IGZO gate length gate position |
| url | https://ieeexplore.ieee.org/document/10836807/ |
| work_keys_str_mv | AT yuezhao tcadsimulationstudyofcylindricalverticaldoublesurroundinggateaingaznofetsandgeometricparameteroptimization AT lihuaxu tcadsimulationstudyofcylindricalverticaldoublesurroundinggateaingaznofetsandgeometricparameteroptimization AT chuankechen tcadsimulationstudyofcylindricalverticaldoublesurroundinggateaingaznofetsandgeometricparameteroptimization AT xufanli tcadsimulationstudyofcylindricalverticaldoublesurroundinggateaingaznofetsandgeometricparameteroptimization AT kexinshang tcadsimulationstudyofcylindricalverticaldoublesurroundinggateaingaznofetsandgeometricparameteroptimization AT digeng tcadsimulationstudyofcylindricalverticaldoublesurroundinggateaingaznofetsandgeometricparameteroptimization AT lingfeiwang tcadsimulationstudyofcylindricalverticaldoublesurroundinggateaingaznofetsandgeometricparameteroptimization AT lingli tcadsimulationstudyofcylindricalverticaldoublesurroundinggateaingaznofetsandgeometricparameteroptimization |