rule4ml: an open-source tool for resource utilization and latency estimation for ML models on FPGA
Implementing machine learning (ML) models on field-programmable gate arrays (FPGAs) is becoming increasingly popular across various domains as a low-latency and low-power solution that helps manage large data rates generated by continuously improving detectors. However, developing ML models for FPGA...
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IOP Publishing
2025-01-01
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| Series: | Machine Learning: Science and Technology |
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| Online Access: | https://doi.org/10.1088/2632-2153/ada71c |
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| author | Mohammad Mehdi Rahimifar Hamza Ezzaoui Rahali Audrey C Therrien |
| author_facet | Mohammad Mehdi Rahimifar Hamza Ezzaoui Rahali Audrey C Therrien |
| author_sort | Mohammad Mehdi Rahimifar |
| collection | DOAJ |
| description | Implementing machine learning (ML) models on field-programmable gate arrays (FPGAs) is becoming increasingly popular across various domains as a low-latency and low-power solution that helps manage large data rates generated by continuously improving detectors. However, developing ML models for FPGAs is time-consuming, as optimization requires synthesis to evaluate FPGA area and latency, making the process slow and repetitive. This paper introduces a novel method to predict the resource utilization and inference latency of neural networks (NNs) before their synthesis and implementation on FPGA. We leverage HLS4ML, a tool-flow that helps translate NNs into high-level synthesis (HLS) code, to synthesize a diverse dataset of NN architectures and train resource utilization and inference latency predictors. While HLS4ML requires full synthesis to obtain resource and latency insights, our method uses trained regression models for immediate pre-synthesis predictions. The prediction models estimate the usage of block RAM, digital signal processors, flip-flops, and look-Up tables, as well as the inference clock cycles. The predictors were evaluated on both synthetic and existing benchmark architectures and demonstrated high accuracy with R ^2 scores ranging between 0.8 and 0.98 on the validation set and sMAPE values between 10% and 30%. Overall, our approach provides valuable preliminary insights, enabling users to quickly assess the feasibility and efficiency of NNs on FPGAs, accelerating the development and deployment processes. The open-source repository can be found at https://github.com/IMPETUS-UdeS/rule4ml , while the datasets are publicly available at https://borealisdata.ca/dataverse/rule4ml . |
| format | Article |
| id | doaj-art-6511eebe16ef44dc8e3f709b2d1f7d9d |
| institution | Kabale University |
| issn | 2632-2153 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IOP Publishing |
| record_format | Article |
| series | Machine Learning: Science and Technology |
| spelling | doaj-art-6511eebe16ef44dc8e3f709b2d1f7d9d2025-02-06T12:30:38ZengIOP PublishingMachine Learning: Science and Technology2632-21532025-01-016101500910.1088/2632-2153/ada71crule4ml: an open-source tool for resource utilization and latency estimation for ML models on FPGAMohammad Mehdi Rahimifar0https://orcid.org/0000-0002-6582-8322Hamza Ezzaoui Rahali1https://orcid.org/0000-0002-0352-725XAudrey C Therrien2https://orcid.org/0000-0001-6698-8400Interdisciplinary Institute for Technological Innovation - 3IT , Université de Sherbrooke, Sherbrooke, Québec, CanadaInterdisciplinary Institute for Technological Innovation - 3IT , Université de Sherbrooke, Sherbrooke, Québec, CanadaInterdisciplinary Institute for Technological Innovation - 3IT , Université de Sherbrooke, Sherbrooke, Québec, CanadaImplementing machine learning (ML) models on field-programmable gate arrays (FPGAs) is becoming increasingly popular across various domains as a low-latency and low-power solution that helps manage large data rates generated by continuously improving detectors. However, developing ML models for FPGAs is time-consuming, as optimization requires synthesis to evaluate FPGA area and latency, making the process slow and repetitive. This paper introduces a novel method to predict the resource utilization and inference latency of neural networks (NNs) before their synthesis and implementation on FPGA. We leverage HLS4ML, a tool-flow that helps translate NNs into high-level synthesis (HLS) code, to synthesize a diverse dataset of NN architectures and train resource utilization and inference latency predictors. While HLS4ML requires full synthesis to obtain resource and latency insights, our method uses trained regression models for immediate pre-synthesis predictions. The prediction models estimate the usage of block RAM, digital signal processors, flip-flops, and look-Up tables, as well as the inference clock cycles. The predictors were evaluated on both synthetic and existing benchmark architectures and demonstrated high accuracy with R ^2 scores ranging between 0.8 and 0.98 on the validation set and sMAPE values between 10% and 30%. Overall, our approach provides valuable preliminary insights, enabling users to quickly assess the feasibility and efficiency of NNs on FPGAs, accelerating the development and deployment processes. The open-source repository can be found at https://github.com/IMPETUS-UdeS/rule4ml , while the datasets are publicly available at https://borealisdata.ca/dataverse/rule4ml .https://doi.org/10.1088/2632-2153/ada71cmachine learningdeep learningneural networksFPGAoptimizationEdgeML |
| spellingShingle | Mohammad Mehdi Rahimifar Hamza Ezzaoui Rahali Audrey C Therrien rule4ml: an open-source tool for resource utilization and latency estimation for ML models on FPGA Machine Learning: Science and Technology machine learning deep learning neural networks FPGA optimization EdgeML |
| title | rule4ml: an open-source tool for resource utilization and latency estimation for ML models on FPGA |
| title_full | rule4ml: an open-source tool for resource utilization and latency estimation for ML models on FPGA |
| title_fullStr | rule4ml: an open-source tool for resource utilization and latency estimation for ML models on FPGA |
| title_full_unstemmed | rule4ml: an open-source tool for resource utilization and latency estimation for ML models on FPGA |
| title_short | rule4ml: an open-source tool for resource utilization and latency estimation for ML models on FPGA |
| title_sort | rule4ml an open source tool for resource utilization and latency estimation for ml models on fpga |
| topic | machine learning deep learning neural networks FPGA optimization EdgeML |
| url | https://doi.org/10.1088/2632-2153/ada71c |
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