Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application
This paper proposes a circuit capable of incorporating buffered delays in the order of picoseconds. To study our proposed circuit in the profound way, we have also explored our proposed circuit using emerging technologies such as FinFET and CNFET. Comparisons between these technologies have been mad...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2015-01-01
|
| Series: | Active and Passive Electronic Components |
| Online Access: | http://dx.doi.org/10.1155/2015/920508 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832566129862639616 |
|---|---|
| author | Amit Krishna Dwivedi Kumar Abhijeet Urma Aminul Islam |
| author_facet | Amit Krishna Dwivedi Kumar Abhijeet Urma Aminul Islam |
| author_sort | Amit Krishna Dwivedi |
| collection | DOAJ |
| description | This paper proposes a circuit capable of incorporating buffered delays in the order of picoseconds. To study our proposed circuit in the profound way, we have also explored our proposed circuit using emerging technologies such as FinFET and CNFET. Comparisons between these technologies have been made in terms of different parameters such as duration of incorporated delays (pulse width) and its variability with supply voltages. Further, this paper also proposes a trigger pulse generator by utilizing proposed buffered delay circuit as its basic element. Parametric results obtained for the proposed trigger pulse generator match different application specific requirements. These applications are also mentioned in this paper. The proposed trigger pulse generator requires very low supply voltage (700 mV) and also proves its effectiveness in terms of tunability of pulse width of the generated pulses. The modeling of the circuit has been done using Verilog and the simulation results are extensively verified using SPICE. |
| format | Article |
| id | doaj-art-5a5e1bd94bae4f8b899fb070da53ecb4 |
| institution | Kabale University |
| issn | 0882-7516 1563-5031 |
| language | English |
| publishDate | 2015-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Active and Passive Electronic Components |
| spelling | doaj-art-5a5e1bd94bae4f8b899fb070da53ecb42025-02-03T01:04:57ZengWileyActive and Passive Electronic Components0882-75161563-50312015-01-01201510.1155/2015/920508920508Trigger Pulse Generator Using Proposed Buffered Delay Model and Its ApplicationAmit Krishna Dwivedi0Kumar Abhijeet Urma1Aminul Islam2Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand 835215, IndiaDepartment of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand 835215, IndiaDepartment of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand 835215, IndiaThis paper proposes a circuit capable of incorporating buffered delays in the order of picoseconds. To study our proposed circuit in the profound way, we have also explored our proposed circuit using emerging technologies such as FinFET and CNFET. Comparisons between these technologies have been made in terms of different parameters such as duration of incorporated delays (pulse width) and its variability with supply voltages. Further, this paper also proposes a trigger pulse generator by utilizing proposed buffered delay circuit as its basic element. Parametric results obtained for the proposed trigger pulse generator match different application specific requirements. These applications are also mentioned in this paper. The proposed trigger pulse generator requires very low supply voltage (700 mV) and also proves its effectiveness in terms of tunability of pulse width of the generated pulses. The modeling of the circuit has been done using Verilog and the simulation results are extensively verified using SPICE.http://dx.doi.org/10.1155/2015/920508 |
| spellingShingle | Amit Krishna Dwivedi Kumar Abhijeet Urma Aminul Islam Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application Active and Passive Electronic Components |
| title | Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application |
| title_full | Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application |
| title_fullStr | Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application |
| title_full_unstemmed | Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application |
| title_short | Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application |
| title_sort | trigger pulse generator using proposed buffered delay model and its application |
| url | http://dx.doi.org/10.1155/2015/920508 |
| work_keys_str_mv | AT amitkrishnadwivedi triggerpulsegeneratorusingproposedbuffereddelaymodelanditsapplication AT kumarabhijeeturma triggerpulsegeneratorusingproposedbuffereddelaymodelanditsapplication AT aminulislam triggerpulsegeneratorusingproposedbuffereddelaymodelanditsapplication |