A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance

We propose a fast data relay (FDR) mechanism to enhance existing CGRA (coarse-grained reconfigurable architecture). FDR can not only provide multicycle data transmission in concurrent with computations but also convert resource-demanding inter-processing-element global data accesses into local data...

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Bibliographic Details
Main Authors: Lu Wan, Chen Dong, Deming Chen
Format: Article
Language:English
Published: Wiley 2012-01-01
Series:International Journal of Reconfigurable Computing
Online Access:http://dx.doi.org/10.1155/2012/163542
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