Hardware-accelerated real-time IP flow measurement method for multi-core architecture

Hardware-accelerated real-time IP flow measurement method for multi-core architecture

A hardware-accelerated real-time IP flow measurement method for multi-core architecture was proposed. IP datagrams were captured at wire speed of OC-192 links by FPGA. Data records were load balanced to the corresponding core-affinitive buffer queues to each processor core at flow level. Multi-stage...

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Bibliographic Details
Main Authors: ZHU Chao1, XIE Ying-ke1, WANG Jian-dong1, ZHAO Zi-li1, HAN Cheng-de1
Format: Article
Language:zho
Published: Editorial Department of Journal on Communications 2008-01-01
Series:Tongxin xuebao
Subjects:
computer architecture
network measurement
hardware acceleration
IP flow
multi-core architecture
FPGA
Online Access:http://www.joconline.com.cn/zh/article/74652934/
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