Hardware-Software Stitching Algorithm in Lightweight Q-Learning System on Chip (SoC) for Shortest Path Optimization

Hardware-Software Stitching Algorithm in Lightweight Q-Learning System on Chip (SoC) for Shortest Path Optimization

This paper presents a novel hardware-software co-design approach to accelerate Q-learning algorithms using a RISC-V-based System-on-Chip (SoC) design. We introduce a maze-stitching algorithm that enables efficient solving of large, complex mazes by decomposing them into smaller sub-mazes and thus ca...

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Bibliographic Details
Main Authors: Yahwista Salomo, Infall Syafalni, Nana Sutisna, Trio Adiono
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
Subjects:
RISC-V
Q-learning
hardware accelerator
system-on-chip
hardware-software co-design
Online Access:https://ieeexplore.ieee.org/document/11030563/
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