Area-Efficient Variable-Gain Delta-Sigma Modulator Achieving 11.5-dB Dynamic Range Improvement by Sharing Capacitors in the First-Stage Integrator
This paper presents an area-efficient variable-gain delta-sigma modulator (VGDSM) that shares the sampling, feedback, and integrating capacitors in the first-stage integrator while maintaining a constant sum of their capacitance values. By adjusting the VGDSM gain through sharing these capacitors, t...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/11029266/ |
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| Summary: | This paper presents an area-efficient variable-gain delta-sigma modulator (VGDSM) that shares the sampling, feedback, and integrating capacitors in the first-stage integrator while maintaining a constant sum of their capacitance values. By adjusting the VGDSM gain through sharing these capacitors, the proposed architecture increases the dynamic range (DR) compared to the fixed-gain delta-sigma modulator, while improving area efficiency compared to conventional VGDSM that use dummy sampling capacitors with fixed-valued feedback and integrating capacitors. For each VGDSM gain, the capacitances of the three capacitors were determined considering three design constraints related to area, noise, and linearity, respectively. Compared to the conventional VGDSM that includes dummy capacitors, this approach reduces the total capacitance of the first-stage integrator by 46.7%. Implemented in 180-nm CMOS technology, the modulator increased DR by 11.5 dB, to 100.4 dB. The active chip area is 0.301 mm2, and with a 1.8-V supply, the power consumption is <inline-formula> <tex-math notation="LaTeX">$732.8~\mu $ </tex-math></inline-formula>W, achieving a Schreier figure-of-merit of 175.7 dB. |
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| ISSN: | 2169-3536 |