Meta‐stability immunity technique for high speed SAR ADCs

An 8‐bit 4 GS/s 8‐channel time‐interleaved successive approximation register (SAR) analogue‐to‐digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta‐stability immunity technique is proposed, which utilises pre‐installation to eliminate uncertain decision. The t...

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Main Authors: L. Qiu, K. Tang, Y.J. Zheng, L. Siek
Format: Article
Language:English
Published: Wiley 2017-03-01
Series:Electronics Letters
Subjects:
Online Access:https://doi.org/10.1049/el.2016.4001
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author L. Qiu
K. Tang
Y.J. Zheng
L. Siek
author_facet L. Qiu
K. Tang
Y.J. Zheng
L. Siek
author_sort L. Qiu
collection DOAJ
description An 8‐bit 4 GS/s 8‐channel time‐interleaved successive approximation register (SAR) analogue‐to‐digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta‐stability immunity technique is proposed, which utilises pre‐installation to eliminate uncertain decision. The technique has negligible design overhead in terms of power and silicon area. The ADC chip was fabricated in a 65 nm CMOS technology. It achieves an ENOB of 7.45 bits, with 48 mW power consumption and an area of 0.075 mm2.
format Article
id doaj-art-4bd4d885daa84794b455d63ac8a5b941
institution Kabale University
issn 0013-5194
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language English
publishDate 2017-03-01
publisher Wiley
record_format Article
series Electronics Letters
spelling doaj-art-4bd4d885daa84794b455d63ac8a5b9412025-02-05T12:30:42ZengWileyElectronics Letters0013-51941350-911X2017-03-0153530030210.1049/el.2016.4001Meta‐stability immunity technique for high speed SAR ADCsL. Qiu0K. Tang1Y.J. Zheng2L. Siek3School of Electrical and Electronic EngineeringNanyang Technological University50 Nanyang AvenueSingaporeSchool of Electrical and Electronic EngineeringNanyang Technological University50 Nanyang AvenueSingaporeSchool of Electrical and Electronic EngineeringNanyang Technological University50 Nanyang AvenueSingaporeSchool of Electrical and Electronic EngineeringNanyang Technological University50 Nanyang AvenueSingaporeAn 8‐bit 4 GS/s 8‐channel time‐interleaved successive approximation register (SAR) analogue‐to‐digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta‐stability immunity technique is proposed, which utilises pre‐installation to eliminate uncertain decision. The technique has negligible design overhead in terms of power and silicon area. The ADC chip was fabricated in a 65 nm CMOS technology. It achieves an ENOB of 7.45 bits, with 48 mW power consumption and an area of 0.075 mm2.https://doi.org/10.1049/el.2016.4001metastability immunity techniquehigh speed SAR ADCtime‐interleaved successive approximation registeranalogue‐to‐digital converterENOBeffective number of bits
spellingShingle L. Qiu
K. Tang
Y.J. Zheng
L. Siek
Meta‐stability immunity technique for high speed SAR ADCs
Electronics Letters
metastability immunity technique
high speed SAR ADC
time‐interleaved successive approximation register
analogue‐to‐digital converter
ENOB
effective number of bits
title Meta‐stability immunity technique for high speed SAR ADCs
title_full Meta‐stability immunity technique for high speed SAR ADCs
title_fullStr Meta‐stability immunity technique for high speed SAR ADCs
title_full_unstemmed Meta‐stability immunity technique for high speed SAR ADCs
title_short Meta‐stability immunity technique for high speed SAR ADCs
title_sort meta stability immunity technique for high speed sar adcs
topic metastability immunity technique
high speed SAR ADC
time‐interleaved successive approximation register
analogue‐to‐digital converter
ENOB
effective number of bits
url https://doi.org/10.1049/el.2016.4001
work_keys_str_mv AT lqiu metastabilityimmunitytechniqueforhighspeedsaradcs
AT ktang metastabilityimmunitytechniqueforhighspeedsaradcs
AT yjzheng metastabilityimmunitytechniqueforhighspeedsaradcs
AT lsiek metastabilityimmunitytechniqueforhighspeedsaradcs