Meta‐stability immunity technique for high speed SAR ADCs
An 8‐bit 4 GS/s 8‐channel time‐interleaved successive approximation register (SAR) analogue‐to‐digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta‐stability immunity technique is proposed, which utilises pre‐installation to eliminate uncertain decision. The t...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2017-03-01
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| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/el.2016.4001 |
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| Summary: | An 8‐bit 4 GS/s 8‐channel time‐interleaved successive approximation register (SAR) analogue‐to‐digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta‐stability immunity technique is proposed, which utilises pre‐installation to eliminate uncertain decision. The technique has negligible design overhead in terms of power and silicon area. The ADC chip was fabricated in a 65 nm CMOS technology. It achieves an ENOB of 7.45 bits, with 48 mW power consumption and an area of 0.075 mm2. |
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| ISSN: | 0013-5194 1350-911X |