FPGA Implementation of A∗ Algorithm for Real-Time Path Planning
The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list. To achieve real-time path-planning performance, a hardware accelerator’s architecture called A∗ accelerator has been designed and implemented in f...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2020-01-01
|
| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2020/8896386 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832565990513180672 |
|---|---|
| author | Yuzhi Zhou Xi Jin Tianqi Wang |
| author_facet | Yuzhi Zhou Xi Jin Tianqi Wang |
| author_sort | Yuzhi Zhou |
| collection | DOAJ |
| description | The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list. To achieve real-time path-planning performance, a hardware accelerator’s architecture called A∗ accelerator has been designed and implemented in field programmable gate array (FPGA). The specially designed 8-port cache and OPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx Kintex-7 FPGA to evaluate A∗ accelerator. Experiments show that the hardware accelerator achieves 37–75 times performance enhancement relative to software implementation. It is suitable for real-time path-planning applications. |
| format | Article |
| id | doaj-art-4b98fd1f322d4504a08c77dcfa1a7048 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2020-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-4b98fd1f322d4504a08c77dcfa1a70482025-02-03T01:05:18ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092020-01-01202010.1155/2020/88963868896386FPGA Implementation of A∗ Algorithm for Real-Time Path PlanningYuzhi Zhou0Xi Jin1Tianqi Wang2University of Science and Technology of China, Hefei, ChinaUniversity of Science and Technology of China, Hefei, ChinaUniversity of Science and Technology of China, Hefei, ChinaThe traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list. To achieve real-time path-planning performance, a hardware accelerator’s architecture called A∗ accelerator has been designed and implemented in field programmable gate array (FPGA). The specially designed 8-port cache and OPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx Kintex-7 FPGA to evaluate A∗ accelerator. Experiments show that the hardware accelerator achieves 37–75 times performance enhancement relative to software implementation. It is suitable for real-time path-planning applications.http://dx.doi.org/10.1155/2020/8896386 |
| spellingShingle | Yuzhi Zhou Xi Jin Tianqi Wang FPGA Implementation of A∗ Algorithm for Real-Time Path Planning International Journal of Reconfigurable Computing |
| title | FPGA Implementation of A∗ Algorithm for Real-Time Path Planning |
| title_full | FPGA Implementation of A∗ Algorithm for Real-Time Path Planning |
| title_fullStr | FPGA Implementation of A∗ Algorithm for Real-Time Path Planning |
| title_full_unstemmed | FPGA Implementation of A∗ Algorithm for Real-Time Path Planning |
| title_short | FPGA Implementation of A∗ Algorithm for Real-Time Path Planning |
| title_sort | fpga implementation of a∗ algorithm for real time path planning |
| url | http://dx.doi.org/10.1155/2020/8896386 |
| work_keys_str_mv | AT yuzhizhou fpgaimplementationofaalgorithmforrealtimepathplanning AT xijin fpgaimplementationofaalgorithmforrealtimepathplanning AT tianqiwang fpgaimplementationofaalgorithmforrealtimepathplanning |