Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques
This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power consumption while using a low-frequency reference of 50...
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10746550/ |
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| author | Teerachot Siriburanon Chunxiao Liu Jianglin Du Robert Bogdan Staszewski |
| author_facet | Teerachot Siriburanon Chunxiao Liu Jianglin Du Robert Bogdan Staszewski |
| author_sort | Teerachot Siriburanon |
| collection | DOAJ |
| description | This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power consumption while using a low-frequency reference of 50 MHz. The passive oversampling PD utilizes a zero-forcing technique for voltage-domain presetting and compensation for both the fractional phase and reference spurs induced by imperfections in the reference waveform and reference-waveform oversampling PD (ROS-PD). The ROS-PD eliminates the conventional power-hungry low-noise buffer for the reference input and reduces the PD noise by increasing the loop correction speed. This promotes low jitter and high efficiency in advanced mm-wave PLLs without relying on the increase of the reference clock frequency to several hundred MHz. The imperfections in the reference waveform and ROS-PD, i.e., harmonic distortion, differential path mismatches, and other nonideality factors, can be programmably compensated by the proposed digital manifold calibration scheme, resulting in low reference spurs. A class-F3 oscillator is used to generate a ~10-GHz signal for the feedback divider along with its third harmonic for the harmonic extractor to generate the ~30-GHz output. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 24–31-GHz output carrier with rms jitter of 237 fs while consuming only 12 mW. This corresponds to a state-of-the-art ADPLL <inline-formula> <tex-math notation="LaTeX">${\mathrm {FoM}}_{\text {jitter-N}}$ </tex-math></inline-formula> of −269 dB in a fractional-N mode. Using a comprehensive digital calibration, the reference spurious tones can be reduced from −33 to −65 dBc. |
| format | Article |
| id | doaj-art-3e9b751d67cb48dc97fdfa60220d5cb9 |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-3e9b751d67cb48dc97fdfa60220d5cb92025-01-25T00:03:21ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-01421222510.1109/OJSSCS.2024.349380310746550Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling TechniquesTeerachot Siriburanon0https://orcid.org/0000-0003-1658-9596Chunxiao Liu1https://orcid.org/0009-0003-2803-7104Jianglin Du2Robert Bogdan Staszewski3https://orcid.org/0000-0001-9848-1129School of Electrical and Electronic Engineering, University College Dublin, Dublin 4, IrelandSchool of Electrical and Electronic Engineering, University College Dublin, Dublin 4, IrelandSchool of Electrical and Electronic Engineering, University College Dublin, Dublin 4, IrelandSchool of Electrical and Electronic Engineering, University College Dublin, Dublin 4, IrelandThis article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power consumption while using a low-frequency reference of 50 MHz. The passive oversampling PD utilizes a zero-forcing technique for voltage-domain presetting and compensation for both the fractional phase and reference spurs induced by imperfections in the reference waveform and reference-waveform oversampling PD (ROS-PD). The ROS-PD eliminates the conventional power-hungry low-noise buffer for the reference input and reduces the PD noise by increasing the loop correction speed. This promotes low jitter and high efficiency in advanced mm-wave PLLs without relying on the increase of the reference clock frequency to several hundred MHz. The imperfections in the reference waveform and ROS-PD, i.e., harmonic distortion, differential path mismatches, and other nonideality factors, can be programmably compensated by the proposed digital manifold calibration scheme, resulting in low reference spurs. A class-F3 oscillator is used to generate a ~10-GHz signal for the feedback divider along with its third harmonic for the harmonic extractor to generate the ~30-GHz output. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 24–31-GHz output carrier with rms jitter of 237 fs while consuming only 12 mW. This corresponds to a state-of-the-art ADPLL <inline-formula> <tex-math notation="LaTeX">${\mathrm {FoM}}_{\text {jitter-N}}$ </tex-math></inline-formula> of −269 dB in a fractional-N mode. Using a comprehensive digital calibration, the reference spurious tones can be reduced from −33 to −65 dBc.https://ieeexplore.ieee.org/document/10746550/All-digital phase-locked loop (ADPLL)fractional-Nlow jitterlow powermillimeter-wave (mmW)reference-sampling PLL (RS-PLL) |
| spellingShingle | Teerachot Siriburanon Chunxiao Liu Jianglin Du Robert Bogdan Staszewski Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques IEEE Open Journal of the Solid-State Circuits Society All-digital phase-locked loop (ADPLL) fractional-N low jitter low power millimeter-wave (mmW) reference-sampling PLL (RS-PLL) |
| title | Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques |
| title_full | Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques |
| title_fullStr | Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques |
| title_full_unstemmed | Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques |
| title_short | Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques |
| title_sort | millimeter wave all digital phase locked loop using reference waveform oversampling techniques |
| topic | All-digital phase-locked loop (ADPLL) fractional-N low jitter low power millimeter-wave (mmW) reference-sampling PLL (RS-PLL) |
| url | https://ieeexplore.ieee.org/document/10746550/ |
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