Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing
In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2017-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2017/7021056 |
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| author | Ali Asghar Muhammad Mazher Iqbal Waqar Ahmed Mujahid Ali Husain Parvez Muhammad Rashid |
| author_facet | Ali Asghar Muhammad Mazher Iqbal Waqar Ahmed Mujahid Ali Husain Parvez Muhammad Rashid |
| author_sort | Ali Asghar |
| collection | DOAJ |
| description | In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. In this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory (SRAM) tables among NPN-equivalent functions, to reduce the area as well as the number of configuration bits. We then propose several methods to improve the existing architecture. A new clustering technique has been proposed which packs NPN-equivalent functions together inside a Configurable Logic Block (CLB). We also make use of a recently proposed high performance Boolean matching algorithm to perform NPN classification. To enhance area savings further, we evaluate the feasibility of more than two LUTs sharing the same SRAM table. Consequently, this work explores the SRAM table sharing approach for a range of LUT sizes (4–7), while varying the cluster sizes (4–16). Experimental results on MCNC benchmark circuits set show an overall area reduction of ~7% while maintaining the same critical path delay. |
| format | Article |
| id | doaj-art-35b3d20091674219b895cea38d590169 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2017-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-35b3d20091674219b895cea38d5901692025-02-03T06:01:18ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092017-01-01201710.1155/2017/70210567021056Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of SharingAli Asghar0Muhammad Mazher Iqbal1Waqar Ahmed2Mujahid Ali3Husain Parvez4Muhammad Rashid5Karachi Institute of Economics and Technology, Karachi, PakistanKarachi Institute of Economics and Technology, Karachi, PakistanKarachi Institute of Economics and Technology, Karachi, PakistanKarachi Institute of Economics and Technology, Karachi, PakistanKarachi Institute of Economics and Technology, Karachi, PakistanUmm Al-Qura University, Makkah, Saudi ArabiaIn modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. In this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory (SRAM) tables among NPN-equivalent functions, to reduce the area as well as the number of configuration bits. We then propose several methods to improve the existing architecture. A new clustering technique has been proposed which packs NPN-equivalent functions together inside a Configurable Logic Block (CLB). We also make use of a recently proposed high performance Boolean matching algorithm to perform NPN classification. To enhance area savings further, we evaluate the feasibility of more than two LUTs sharing the same SRAM table. Consequently, this work explores the SRAM table sharing approach for a range of LUT sizes (4–7), while varying the cluster sizes (4–16). Experimental results on MCNC benchmark circuits set show an overall area reduction of ~7% while maintaining the same critical path delay.http://dx.doi.org/10.1155/2017/7021056 |
| spellingShingle | Ali Asghar Muhammad Mazher Iqbal Waqar Ahmed Mujahid Ali Husain Parvez Muhammad Rashid Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing International Journal of Reconfigurable Computing |
| title | Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing |
| title_full | Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing |
| title_fullStr | Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing |
| title_full_unstemmed | Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing |
| title_short | Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing |
| title_sort | exploring shared sram tables in fpgas for larger luts and higher degree of sharing |
| url | http://dx.doi.org/10.1155/2017/7021056 |
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