Enhanced Performance of New Scaling-Free CORDIC for Memory-Based Fast Fourier Transform Architecture
Coordinate rotation digital computer (CORDIC) algorithm is an iterative method and it performs the vector rotation operation by micro-rotation with scaling operation in each iteration. This study introduces a high-performance power-efficient new scaling-free coordinate rotation digital computer (NSF...
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IEEE
2025-01-01
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| Online Access: | https://ieeexplore.ieee.org/document/10843669/ |
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| author | C. Paramasivam Sandeep Singh Chauhan Veerpratap Meena A. Sreejagathi B. A. V. N. Hasini K. L. K. Kishore T. V. N. G. Vamsikrishna M. Durga Ananta Sai Abdessamad Didi |
| author_facet | C. Paramasivam Sandeep Singh Chauhan Veerpratap Meena A. Sreejagathi B. A. V. N. Hasini K. L. K. Kishore T. V. N. G. Vamsikrishna M. Durga Ananta Sai Abdessamad Didi |
| author_sort | C. Paramasivam |
| collection | DOAJ |
| description | Coordinate rotation digital computer (CORDIC) algorithm is an iterative method and it performs the vector rotation operation by micro-rotation with scaling operation in each iteration. This study introduces a high-performance power-efficient new scaling-free coordinate rotation digital computer (NSF-CORDIC) algorithm to perform vector rotation operation in circular coordinates. The scaling operation required in the existing algorithm has been completely removed by the fourth-order approximation of Taylor series (TS). The number of iterations is reduced by an optimized shift value prediction technique for known and fixed angles, like the twiddle factor angle available in the fast Fourier transform (FFT) algorithm. The angle of convergence (AOC) of the algorithm is 57.1°, and it is extended to 180° using the pre-rotation operation and optimized shift value prediction technique. In addition to that, the new CORDIC cell architecture is designed to perform Taylor series-based iterations. Further, a memory-based FFT architecture is designed using a new CORDIC cell. In the FFT architecture, the CORDIC cell performs all the multiplication of twiddle factor. Therefore, the complex constant multiplier required to execute the twiddle factor multiplication is eliminated. The proposed architectures are implemented in the Zynq-7ZC706 FPGA board using the Vivado EDA tool. The scaling-free CORDIC cell architecture has 31% and 3% slice reduction, 72% and 45% slice delay product reduction, and 38% and 23% power reduction compared to the two different existing scaling-free CORDIC designs. The memory-based FFT architecture has 37.8% and 19.6% slice reduction, 38.4% and 27% slice delay product reduction, and 45% and 34% power reduction compared to the two different existing memory-based FFT architecture. |
| format | Article |
| id | doaj-art-3080e88c4e9449859ceeb83ea269b63b |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-3080e88c4e9449859ceeb83ea269b63b2025-01-31T23:05:04ZengIEEEIEEE Access2169-35362025-01-0113198281984410.1109/ACCESS.2025.353068410843669Enhanced Performance of New Scaling-Free CORDIC for Memory-Based Fast Fourier Transform ArchitectureC. Paramasivam0https://orcid.org/0000-0003-2508-2308Sandeep Singh Chauhan1Veerpratap Meena2https://orcid.org/0000-0002-5910-9778A. Sreejagathi3B. A. V. N. Hasini4K. L. K. Kishore5T. V. N. G. Vamsikrishna6M. Durga Ananta Sai7Abdessamad Didi8https://orcid.org/0000-0003-4225-9232Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru, IndiaDepartment of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru, IndiaDepartment of Electrical Engineering, National Institute of Technology Jamshedpur, Jamshedpur, Jharkhand, IndiaDepartment of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru, IndiaDepartment of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru, IndiaDepartment of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru, IndiaDepartment of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru, IndiaDepartment of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Bengaluru, IndiaNational Energy Center of Nuclear Science and Technology, Rabat, MoroccoCoordinate rotation digital computer (CORDIC) algorithm is an iterative method and it performs the vector rotation operation by micro-rotation with scaling operation in each iteration. This study introduces a high-performance power-efficient new scaling-free coordinate rotation digital computer (NSF-CORDIC) algorithm to perform vector rotation operation in circular coordinates. The scaling operation required in the existing algorithm has been completely removed by the fourth-order approximation of Taylor series (TS). The number of iterations is reduced by an optimized shift value prediction technique for known and fixed angles, like the twiddle factor angle available in the fast Fourier transform (FFT) algorithm. The angle of convergence (AOC) of the algorithm is 57.1°, and it is extended to 180° using the pre-rotation operation and optimized shift value prediction technique. In addition to that, the new CORDIC cell architecture is designed to perform Taylor series-based iterations. Further, a memory-based FFT architecture is designed using a new CORDIC cell. In the FFT architecture, the CORDIC cell performs all the multiplication of twiddle factor. Therefore, the complex constant multiplier required to execute the twiddle factor multiplication is eliminated. The proposed architectures are implemented in the Zynq-7ZC706 FPGA board using the Vivado EDA tool. The scaling-free CORDIC cell architecture has 31% and 3% slice reduction, 72% and 45% slice delay product reduction, and 38% and 23% power reduction compared to the two different existing scaling-free CORDIC designs. The memory-based FFT architecture has 37.8% and 19.6% slice reduction, 38.4% and 27% slice delay product reduction, and 45% and 34% power reduction compared to the two different existing memory-based FFT architecture.https://ieeexplore.ieee.org/document/10843669/Coordinate rotation digital computer (CORDIC)fast Fourier transform (FFT)memory-based FFT architecturenew scaling-free CORIDCmicro-rotationscaling operation |
| spellingShingle | C. Paramasivam Sandeep Singh Chauhan Veerpratap Meena A. Sreejagathi B. A. V. N. Hasini K. L. K. Kishore T. V. N. G. Vamsikrishna M. Durga Ananta Sai Abdessamad Didi Enhanced Performance of New Scaling-Free CORDIC for Memory-Based Fast Fourier Transform Architecture IEEE Access Coordinate rotation digital computer (CORDIC) fast Fourier transform (FFT) memory-based FFT architecture new scaling-free CORIDC micro-rotation scaling operation |
| title | Enhanced Performance of New Scaling-Free CORDIC for Memory-Based Fast Fourier Transform Architecture |
| title_full | Enhanced Performance of New Scaling-Free CORDIC for Memory-Based Fast Fourier Transform Architecture |
| title_fullStr | Enhanced Performance of New Scaling-Free CORDIC for Memory-Based Fast Fourier Transform Architecture |
| title_full_unstemmed | Enhanced Performance of New Scaling-Free CORDIC for Memory-Based Fast Fourier Transform Architecture |
| title_short | Enhanced Performance of New Scaling-Free CORDIC for Memory-Based Fast Fourier Transform Architecture |
| title_sort | enhanced performance of new scaling free cordic for memory based fast fourier transform architecture |
| topic | Coordinate rotation digital computer (CORDIC) fast Fourier transform (FFT) memory-based FFT architecture new scaling-free CORIDC micro-rotation scaling operation |
| url | https://ieeexplore.ieee.org/document/10843669/ |
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