A Stepped Gate Oxide Structure for Suppressing Gate-Induced Drain Leakage in Fully Depleted Germanium-on-Insulator Multi-Subchannel Tunneling Field-Effect Transistors
To address the severe gate-induced drain leakage (GIDL) issue in fully depleted germanium-on-insulator (FD-GeOI) multi-subchannel tunneling field-effect transistors (MS TFETs), this paper proposes a stepped gate oxide (SGO) structure. In the off-state, the SGO structure effectively suppresses GIDL b...
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2025-03-01
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| author | Rui Chen Liming Wang Ruizhe Han Keqin Liao Xinlong Shi Peijian Zhang Huiyong Hu |
| author_facet | Rui Chen Liming Wang Ruizhe Han Keqin Liao Xinlong Shi Peijian Zhang Huiyong Hu |
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| description | To address the severe gate-induced drain leakage (GIDL) issue in fully depleted germanium-on-insulator (FD-GeOI) multi-subchannel tunneling field-effect transistors (MS TFETs), this paper proposes a stepped gate oxide (SGO) structure. In the off-state, the SGO structure effectively suppresses GIDL by reducing the electric field intensity at the channel/drain interface while simultaneously decreasing gate capacitance to reduce static power consumption. Based on an accurate device model, a systematic investigation was conducted into the effects of varying the thickness and length of the SGO structure on TFET performance, enabling the optimization of the SGO design. The simulation results demonstrate that, compared to normal MS TFETs, the SGO MS TFET reduces the off-state GIDL current (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>I</mi><mi>off</mi></msub></semantics></math></inline-formula>) from <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>4.6</mn><mo>×</mo><msup><mn>10</mn><mrow><mo>−</mo><mn>7</mn></mrow></msup></mrow></semantics></math></inline-formula> A to <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>2.6</mn><mo>×</mo><msup><mn>10</mn><mrow><mo>−</mo><mn>11</mn></mrow></msup></mrow></semantics></math></inline-formula> A, achieving a maximum improvement of 4.22 orders of magnitude in the on-state-to-off-state current ratio (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mi>I</mi><mi>on</mi></msub><mo>/</mo><msub><mi>I</mi><mi>off</mi></msub></mrow></semantics></math></inline-formula>) and a 28% reduction in subthreshold swing (SS). Furthermore, compared to lightly doped drain (LDD) MS TFETs, the SGO MS TFET achieves a 32% reduction in total gate capacitance and a 23% enhancement in carrier mobility at the channel/drain interface. This study demonstrates that SGO provides an effective solution for GIDL suppression. |
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| spelling | doaj-art-3036e56d03fd45ae9743a7d3dfd4eaa12025-08-20T02:28:32ZengMDPI AGMicromachines2072-666X2025-03-0116437510.3390/mi16040375A Stepped Gate Oxide Structure for Suppressing Gate-Induced Drain Leakage in Fully Depleted Germanium-on-Insulator Multi-Subchannel Tunneling Field-Effect TransistorsRui Chen0Liming Wang1Ruizhe Han2Keqin Liao3Xinlong Shi4Peijian Zhang5Huiyong Hu6Laboratory of Analog Integrated Circuits, Hangzhou Institute of Technology, Xidian University, Hangzhou 311231, ChinaLaboratory of Analog Integrated Circuits, Hangzhou Institute of Technology, Xidian University, Hangzhou 311231, ChinaLaboratory of Analog Integrated Circuits, Hangzhou Institute of Technology, Xidian University, Hangzhou 311231, ChinaLaboratory of Analog Integrated Circuits, Hangzhou Institute of Technology, Xidian University, Hangzhou 311231, ChinaLaboratory of Analog Integrated Circuits, Hangzhou Institute of Technology, Xidian University, Hangzhou 311231, ChinaNational Laboratory of Analog Integrated Circuits, Chongqing 400060, ChinaLaboratory of Analog Integrated Circuits, Hangzhou Institute of Technology, Xidian University, Hangzhou 311231, ChinaTo address the severe gate-induced drain leakage (GIDL) issue in fully depleted germanium-on-insulator (FD-GeOI) multi-subchannel tunneling field-effect transistors (MS TFETs), this paper proposes a stepped gate oxide (SGO) structure. In the off-state, the SGO structure effectively suppresses GIDL by reducing the electric field intensity at the channel/drain interface while simultaneously decreasing gate capacitance to reduce static power consumption. Based on an accurate device model, a systematic investigation was conducted into the effects of varying the thickness and length of the SGO structure on TFET performance, enabling the optimization of the SGO design. The simulation results demonstrate that, compared to normal MS TFETs, the SGO MS TFET reduces the off-state GIDL current (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>I</mi><mi>off</mi></msub></semantics></math></inline-formula>) from <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>4.6</mn><mo>×</mo><msup><mn>10</mn><mrow><mo>−</mo><mn>7</mn></mrow></msup></mrow></semantics></math></inline-formula> A to <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>2.6</mn><mo>×</mo><msup><mn>10</mn><mrow><mo>−</mo><mn>11</mn></mrow></msup></mrow></semantics></math></inline-formula> A, achieving a maximum improvement of 4.22 orders of magnitude in the on-state-to-off-state current ratio (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mi>I</mi><mi>on</mi></msub><mo>/</mo><msub><mi>I</mi><mi>off</mi></msub></mrow></semantics></math></inline-formula>) and a 28% reduction in subthreshold swing (SS). Furthermore, compared to lightly doped drain (LDD) MS TFETs, the SGO MS TFET achieves a 32% reduction in total gate capacitance and a 23% enhancement in carrier mobility at the channel/drain interface. This study demonstrates that SGO provides an effective solution for GIDL suppression.https://www.mdpi.com/2072-666X/16/4/375FD-GeOITFETGIDLmulti-subchannelstepped gate oxide |
| spellingShingle | Rui Chen Liming Wang Ruizhe Han Keqin Liao Xinlong Shi Peijian Zhang Huiyong Hu A Stepped Gate Oxide Structure for Suppressing Gate-Induced Drain Leakage in Fully Depleted Germanium-on-Insulator Multi-Subchannel Tunneling Field-Effect Transistors Micromachines FD-GeOI TFET GIDL multi-subchannel stepped gate oxide |
| title | A Stepped Gate Oxide Structure for Suppressing Gate-Induced Drain Leakage in Fully Depleted Germanium-on-Insulator Multi-Subchannel Tunneling Field-Effect Transistors |
| title_full | A Stepped Gate Oxide Structure for Suppressing Gate-Induced Drain Leakage in Fully Depleted Germanium-on-Insulator Multi-Subchannel Tunneling Field-Effect Transistors |
| title_fullStr | A Stepped Gate Oxide Structure for Suppressing Gate-Induced Drain Leakage in Fully Depleted Germanium-on-Insulator Multi-Subchannel Tunneling Field-Effect Transistors |
| title_full_unstemmed | A Stepped Gate Oxide Structure for Suppressing Gate-Induced Drain Leakage in Fully Depleted Germanium-on-Insulator Multi-Subchannel Tunneling Field-Effect Transistors |
| title_short | A Stepped Gate Oxide Structure for Suppressing Gate-Induced Drain Leakage in Fully Depleted Germanium-on-Insulator Multi-Subchannel Tunneling Field-Effect Transistors |
| title_sort | stepped gate oxide structure for suppressing gate induced drain leakage in fully depleted germanium on insulator multi subchannel tunneling field effect transistors |
| topic | FD-GeOI TFET GIDL multi-subchannel stepped gate oxide |
| url | https://www.mdpi.com/2072-666X/16/4/375 |
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