Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs
We present a method for implementing high speed finite impulse response (FIR) filters on field programmable gate arrays (FPGAs). Our algorithm is a multiplierless technique where fixed coefficient multipliers are replaced with a series of add and shift operations. The first phase of our algorithm us...
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| Format: | Article |
| Language: | English |
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Wiley
2010-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2010/697625 |
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| _version_ | 1832550050849357824 |
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| author | Shahnam Mirzaei Ryan Kastner Anup Hosangadi |
| author_facet | Shahnam Mirzaei Ryan Kastner Anup Hosangadi |
| author_sort | Shahnam Mirzaei |
| collection | DOAJ |
| description | We present a method for implementing high speed finite impulse
response (FIR) filters on field programmable gate arrays (FPGAs).
Our algorithm is a multiplierless technique where fixed
coefficient multipliers are replaced with a series of add and
shift operations. The first phase of our algorithm uses registered
adders and hardwired shifts. Here, a modified common subexpression
elimination (CSE) algorithm reduces the number of adders while
maintaining performance. The second phase optimizes routing delay
using prelayout wire length estimation techniques to improve the
final placed and routed design. The optimization target platforms
are Xilinx Virtex FPGA devices where we compare the implementation
results with those produced by Xilinx Coregen, which is based on
distributed arithmetic (DA). We observed up to 50% reduction
in the number of slices and up to 75% reduction in the number
of look up tables (LUTs) for fully parallel implementations
compared to DA method. Also, there is 50% reduction in the
total dynamic power consumption of the filters. Our designs
perform up to 27% faster than the multiply accumulate (MAC)
filters implemented by Xilinx Coregen tool using DSP blocks. For
placement, there is a saving up to 20% in number of routing
channels. This results in lower congestion and up to 8%
reduction in average wirelength. |
| format | Article |
| id | doaj-art-2887d08ebd124d47891b07fbdaa68acf |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2010-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-2887d08ebd124d47891b07fbdaa68acf2025-02-03T06:07:48ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092010-01-01201010.1155/2010/697625697625Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAsShahnam Mirzaei0Ryan Kastner1Anup Hosangadi2Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USACadence Design Systems, University of California, San Diego, CA 95134, USADepartment of Computer Science and Engineering, Cadence, La Jolla, CA 92093, USAWe present a method for implementing high speed finite impulse response (FIR) filters on field programmable gate arrays (FPGAs). Our algorithm is a multiplierless technique where fixed coefficient multipliers are replaced with a series of add and shift operations. The first phase of our algorithm uses registered adders and hardwired shifts. Here, a modified common subexpression elimination (CSE) algorithm reduces the number of adders while maintaining performance. The second phase optimizes routing delay using prelayout wire length estimation techniques to improve the final placed and routed design. The optimization target platforms are Xilinx Virtex FPGA devices where we compare the implementation results with those produced by Xilinx Coregen, which is based on distributed arithmetic (DA). We observed up to 50% reduction in the number of slices and up to 75% reduction in the number of look up tables (LUTs) for fully parallel implementations compared to DA method. Also, there is 50% reduction in the total dynamic power consumption of the filters. Our designs perform up to 27% faster than the multiply accumulate (MAC) filters implemented by Xilinx Coregen tool using DSP blocks. For placement, there is a saving up to 20% in number of routing channels. This results in lower congestion and up to 8% reduction in average wirelength.http://dx.doi.org/10.1155/2010/697625 |
| spellingShingle | Shahnam Mirzaei Ryan Kastner Anup Hosangadi Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs International Journal of Reconfigurable Computing |
| title | Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs |
| title_full | Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs |
| title_fullStr | Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs |
| title_full_unstemmed | Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs |
| title_short | Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs |
| title_sort | layout aware optimization of high speed fixed coefficient fir filters for fpgas |
| url | http://dx.doi.org/10.1155/2010/697625 |
| work_keys_str_mv | AT shahnammirzaei layoutawareoptimizationofhighspeedfixedcoefficientfirfiltersforfpgas AT ryankastner layoutawareoptimizationofhighspeedfixedcoefficientfirfiltersforfpgas AT anuphosangadi layoutawareoptimizationofhighspeedfixedcoefficientfirfiltersforfpgas |