Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory
Capacitorless DRAM architectures based on Back-End-of-Line (BEOL)-transistors are promising for long-retention, high-density and low-power 3D DRAM solutions due to its low leakage, operational flexibility, and monolithic integration capability. Different from classical silicon-based devices, in-dept...
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2024-01-01
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| author | Lihua Xu Kaifei Chen Zhi Li Yue Zhao Lingfei Wang Ling Li |
| author_facet | Lihua Xu Kaifei Chen Zhi Li Yue Zhao Lingfei Wang Ling Li |
| author_sort | Lihua Xu |
| collection | DOAJ |
| description | Capacitorless DRAM architectures based on Back-End-of-Line (BEOL)-transistors are promising for long-retention, high-density and low-power 3D DRAM solutions due to its low leakage, operational flexibility, and monolithic integration capability. Different from classical silicon-based devices, in-depth studies on the performances of nanoscale multi-gate transistors (e.g., a-InGaZnO-FET) are still barely conducted for physical description, due to the complicated multi-gating principle, finite-size effects on transport, increased variation sources and enlarged parasitic effect. Hence, high-performance multi-nanoscale (down to <inline-formula> <tex-math notation="LaTeX">$\sim ~50$ </tex-math></inline-formula> nm) dual-gate a-IGZO transistors are fabricated, and a physical compact model is developed based on the surface potential for dual-gated coupling and the disordered transport with finite-size-correction. The short channel behaviors on sub-threshold swing, mobility and threshold voltage are investigated, and contact effects are validated by the transfer-line method (TLM). Regarding the specific challenge of dual-gate alignment, possible misalignment and parasitic effects on multi-device fluctuations are important of large-scale circuit design and analyzed by TCAD simulations. Besides, the bias-temperature instability (BTI) has been comprehensively investigated. In awareness of the above effects, this model bridges fabrication-based material properties and structural parameters, assisting in a threshold fluctuation-resistant operation scheme for capacitorless multi-bit memory, showing a great potential in future monolithic integration circuit design using BEOL-transistor. |
| format | Article |
| id | doaj-art-27628b7175064d0a8c61579e8b5c3885 |
| institution | Kabale University |
| issn | 2168-6734 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
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| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-27628b7175064d0a8c61579e8b5c38852025-01-29T00:00:16ZengIEEEIEEE Journal of the Electron Devices Society2168-67342024-01-011235936410.1109/JEDS.2024.339341810508593Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless MemoryLihua Xu0https://orcid.org/0000-0003-2425-0170Kaifei Chen1Zhi Li2https://orcid.org/0009-0000-9649-7338Yue Zhao3https://orcid.org/0009-0000-7648-429XLingfei Wang4https://orcid.org/0000-0003-3579-8406Ling Li5https://orcid.org/0000-0002-7622-8752School of Microelectronics, University of Science and Technology of China, Hefei, ChinaState Key Lab of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaState Key Lab of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaState Key Lab of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaState Key Lab of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaState Key Lab of Fabrication Technologies for Integrated Circuits, Institute of Microelectronics of Chinese Academy of Sciences, Beijing, ChinaCapacitorless DRAM architectures based on Back-End-of-Line (BEOL)-transistors are promising for long-retention, high-density and low-power 3D DRAM solutions due to its low leakage, operational flexibility, and monolithic integration capability. Different from classical silicon-based devices, in-depth studies on the performances of nanoscale multi-gate transistors (e.g., a-InGaZnO-FET) are still barely conducted for physical description, due to the complicated multi-gating principle, finite-size effects on transport, increased variation sources and enlarged parasitic effect. Hence, high-performance multi-nanoscale (down to <inline-formula> <tex-math notation="LaTeX">$\sim ~50$ </tex-math></inline-formula> nm) dual-gate a-IGZO transistors are fabricated, and a physical compact model is developed based on the surface potential for dual-gated coupling and the disordered transport with finite-size-correction. The short channel behaviors on sub-threshold swing, mobility and threshold voltage are investigated, and contact effects are validated by the transfer-line method (TLM). Regarding the specific challenge of dual-gate alignment, possible misalignment and parasitic effects on multi-device fluctuations are important of large-scale circuit design and analyzed by TCAD simulations. Besides, the bias-temperature instability (BTI) has been comprehensively investigated. In awareness of the above effects, this model bridges fabrication-based material properties and structural parameters, assisting in a threshold fluctuation-resistant operation scheme for capacitorless multi-bit memory, showing a great potential in future monolithic integration circuit design using BEOL-transistor.https://ieeexplore.ieee.org/document/10508593/BTIcompact modelcontact effectsDRAMindependent dual gate a-IGZO-FETdisorder semiconductor |
| spellingShingle | Lihua Xu Kaifei Chen Zhi Li Yue Zhao Lingfei Wang Ling Li Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory IEEE Journal of the Electron Devices Society BTI compact model contact effects DRAM independent dual gate a-IGZO-FET disorder semiconductor |
| title | Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory |
| title_full | Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory |
| title_fullStr | Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory |
| title_full_unstemmed | Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory |
| title_short | Physics-Based Compact Model of Independent Dual-Gate BEOL-Transistors for Reliable Capacitorless Memory |
| title_sort | physics based compact model of independent dual gate beol transistors for reliable capacitorless memory |
| topic | BTI compact model contact effects DRAM independent dual gate a-IGZO-FET disorder semiconductor |
| url | https://ieeexplore.ieee.org/document/10508593/ |
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