3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans
We propose new 3D 2-layer and 3-layer NoC architectures that utilize homogeneous regular mesh networks on a separate layer and one or two heterogeneous floorplanning layers. These architectures combine the benefits of compact heterogeneous floorplans and of regular mesh networks. To demonstrate thes...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2010-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2010/603059 |
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| Summary: | We propose new 3D 2-layer and 3-layer NoC architectures that utilize homogeneous regular mesh
networks on a separate layer and one or two heterogeneous
floorplanning layers. These architectures combine the benefits
of compact heterogeneous floorplans and of regular mesh networks.
To demonstrate these benefits, a design methodology that
integrates floorplanning, routers assignment, and cycle-accurate
NoC simulation is proposed. The implementation of the NoC on
a separate layer offers an additional area that may be utilized to
improve the network performance by increasing the number of
virtual channels, buffers size, or mesh size. Experimental results
show that increasing the number of virtual channels rather than
the buffers size has a higher impact on network performance.
Increasing the mesh size can significantly improve the network
performance under the assumption that the clock frequency is
given by the length of the physical links. In addition, the 3-layer
architecture can offer significantly better network performance
compared to the 2-layer architecture. |
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| ISSN: | 1687-7195 1687-7209 |