Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes
When developing a technology based on single-photon avalanche diodes (SPADs), the SPAD characterization is mandatory to debug, optimize and monitor the microfabrication process. This is especially true for the development of SPAD arrays 3D integrated with CMOS readout electronics, where SPAD testing...
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IEEE
2024-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10414786/ |
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| author | Samuel Parent Frederic Vachon Valerie Gauthier Steve Lamoureux Alexandre Paquette Jacob Deschamps Tommy Rossignol Nicolas Roy Philippe Arsenault Henri Dautet Serge A. Charlebois Jean-Francois Pratte |
| author_facet | Samuel Parent Frederic Vachon Valerie Gauthier Steve Lamoureux Alexandre Paquette Jacob Deschamps Tommy Rossignol Nicolas Roy Philippe Arsenault Henri Dautet Serge A. Charlebois Jean-Francois Pratte |
| author_sort | Samuel Parent |
| collection | DOAJ |
| description | When developing a technology based on single-photon avalanche diodes (SPADs), the SPAD characterization is mandatory to debug, optimize and monitor the microfabrication process. This is especially true for the development of SPAD arrays 3D integrated with CMOS readout electronics, where SPAD testing is required to qualify the process, independently from the final CMOS readout circuit. This work reports on a characterization and monitoring platform dedicated to SPAD testing at die and wafer level, in the context of a 3D SPAD technology development. The platform relies on a dedicated integrated circuit made in a standard CMOS technology and used in different configurations from a prototype printed circuit board (die-level testing) to active probe cards (wafer-level mapping). The platform gives full access to SPAD characteristics in Geiger mode such as the dark noise, photon detection efficiency and timing resolution. The integrated circuit and its configuration are described in detail as well as results obtained on different SPAD test structures. In particular, the dark count rate mapping demonstrates the benefits of testing SPADs at wafer level at the R&D stage. |
| format | Article |
| id | doaj-art-227b16494c96405e875220c6e2c1c4e0 |
| institution | Kabale University |
| issn | 2168-6734 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
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| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-227b16494c96405e875220c6e2c1c4e02025-01-28T00:00:30ZengIEEEIEEE Journal of the Electron Devices Society2168-67342024-01-011212713710.1109/JEDS.2024.335908810414786Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche DiodesSamuel Parent0https://orcid.org/0000-0003-4992-9489Frederic Vachon1https://orcid.org/0000-0002-6976-6624Valerie Gauthier2Steve Lamoureux3https://orcid.org/0000-0003-2146-777XAlexandre Paquette4Jacob Deschamps5Tommy Rossignol6https://orcid.org/0000-0002-9270-9193Nicolas Roy7https://orcid.org/0000-0002-4718-210XPhilippe Arsenault8https://orcid.org/0009-0003-0772-1177Henri Dautet9Serge A. Charlebois10https://orcid.org/0000-0001-7857-5056Jean-Francois Pratte11https://orcid.org/0000-0002-8327-3842Department of Electrical and Computer Engineering, Institut Interdisciplinaire d’Innovation Technologique, Sherbrooke, QC, CanadaDepartment of Electrical and Computer Engineering, Institut Interdisciplinaire d’Innovation Technologique, Sherbrooke, QC, CanadaDepartment of Electrical and Computer Engineering, Institut Interdisciplinaire d’Innovation Technologique, Sherbrooke, QC, CanadaDepartment of Electrical and Computer Engineering, Institut Interdisciplinaire d’Innovation Technologique, Sherbrooke, QC, CanadaDepartment of Electrical and Computer Engineering, Institut Interdisciplinaire d’Innovation Technologique, Sherbrooke, QC, CanadaDepartment of Electrical and Computer Engineering, Institut Interdisciplinaire d’Innovation Technologique, Sherbrooke, QC, CanadaDepartment of Electrical and Computer Engineering, Institut Interdisciplinaire d’Innovation Technologique, Sherbrooke, QC, CanadaDepartment of Electrical and Computer Engineering, Institut Interdisciplinaire d’Innovation Technologique, Sherbrooke, QC, CanadaDepartment of Electrical and Computer Engineering, Institut Interdisciplinaire d’Innovation Technologique, Sherbrooke, QC, CanadaDepartment of Electrical and Computer Engineering, Institut Interdisciplinaire d’Innovation Technologique, Sherbrooke, QC, CanadaDepartment of Electrical and Computer Engineering, Institut Interdisciplinaire d’Innovation Technologique, Sherbrooke, QC, CanadaDepartment of Electrical and Computer Engineering, Institut Interdisciplinaire d’Innovation Technologique, Sherbrooke, QC, CanadaWhen developing a technology based on single-photon avalanche diodes (SPADs), the SPAD characterization is mandatory to debug, optimize and monitor the microfabrication process. This is especially true for the development of SPAD arrays 3D integrated with CMOS readout electronics, where SPAD testing is required to qualify the process, independently from the final CMOS readout circuit. This work reports on a characterization and monitoring platform dedicated to SPAD testing at die and wafer level, in the context of a 3D SPAD technology development. The platform relies on a dedicated integrated circuit made in a standard CMOS technology and used in different configurations from a prototype printed circuit board (die-level testing) to active probe cards (wafer-level mapping). The platform gives full access to SPAD characteristics in Geiger mode such as the dark noise, photon detection efficiency and timing resolution. The integrated circuit and its configuration are described in detail as well as results obtained on different SPAD test structures. In particular, the dark count rate mapping demonstrates the benefits of testing SPADs at wafer level at the R&D stage.https://ieeexplore.ieee.org/document/10414786/Active probe cardphoton-to-digital converterprocess control monitoringsilicon photomultipliersingle-photon avalanche diodewafer-level testing |
| spellingShingle | Samuel Parent Frederic Vachon Valerie Gauthier Steve Lamoureux Alexandre Paquette Jacob Deschamps Tommy Rossignol Nicolas Roy Philippe Arsenault Henri Dautet Serge A. Charlebois Jean-Francois Pratte Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes IEEE Journal of the Electron Devices Society Active probe card photon-to-digital converter process control monitoring silicon photomultiplier single-photon avalanche diode wafer-level testing |
| title | Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes |
| title_full | Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes |
| title_fullStr | Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes |
| title_full_unstemmed | Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes |
| title_short | Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes |
| title_sort | wafer level characterization and monitoring platform for single photon avalanche diodes |
| topic | Active probe card photon-to-digital converter process control monitoring silicon photomultiplier single-photon avalanche diode wafer-level testing |
| url | https://ieeexplore.ieee.org/document/10414786/ |
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