Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOS

The design and the silicon characterization of two mostly digital, low-voltage, energy- and area-efficient Relaxation Digital-to-Analog Converters (ReDACs) in 180nm featuring digital self-calibration and parasitics-induced error suppression are presented and compared in this paper. The first design...

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Bibliographic Details
Main Authors: Roberto Rubino, Francesco Musolino, Pedro Toledo, Yong Chen, Anna Richelli, Paolo S. Crovetti
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
Subjects:
Online Access:https://ieeexplore.ieee.org/document/10829600/
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