Pipeline FFT Architectures Optimized for FPGAs
This paper presents optimized implementations of two different pipeline FFT processors on Xilinx Spartan-3 and Virtex-4 FPGAs. Different optimization techniques and rounding schemes were explored. The implementation results achieved better performance with lower resource usage than prior art. The 16...
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| Format: | Article |
| Language: | English |
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Wiley
2009-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2009/219140 |
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| _version_ | 1832558015241256960 |
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| author | Bin Zhou Yingning Peng David Hwang |
| author_facet | Bin Zhou Yingning Peng David Hwang |
| author_sort | Bin Zhou |
| collection | DOAJ |
| description | This paper presents optimized implementations of two different pipeline FFT processors on Xilinx Spartan-3 and Virtex-4 FPGAs. Different optimization techniques and rounding schemes were explored. The implementation results achieved better performance with lower resource usage than prior art. The 16-bit 1024-point FFT with the R22SDF architecture had a maximum clock frequency of 95.2 MHz and used 2802 slices on the Spartan-3, a throughput per area ratio of 0.034 Msamples/s/slice. The R4SDC architecture ran at 123.8 MHz and used 4409 slices on the Spartan-3, a throughput per area ratio of 0.028 Msamples/s/slice. On Virtex-4, the 16-bit 1024-point R22SDF architecture ran at 235.6 MHz and used 2256 slice, giving a 0.104 Msamples/s/slice ratio; the 16-bit 1024-point R4SDC architecture ran at 219.2 MHz and used 3064 slices, giving a 0.072 Msamples/s/slice ratio. The R22SDF was more efficient than the R4SDC in terms of throughput per area due to a simpler controller and an easier balanced rounding scheme. This paper also shows that balanced stage rounding is an appropriate rounding scheme for pipeline FFT processors. |
| format | Article |
| id | doaj-art-16e9ef25f4ac4a71bb856c4d64635d24 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2009-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-16e9ef25f4ac4a71bb856c4d64635d242025-02-03T01:33:19ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092009-01-01200910.1155/2009/219140219140Pipeline FFT Architectures Optimized for FPGAsBin Zhou0Yingning Peng1David Hwang2Department of Electronic Engineering, Tsinghua University, Beijing 100084, ChinaDepartment of Electronic Engineering, Tsinghua University, Beijing 100084, ChinaDepartment of Electrical and Computer Engineering, George Mason University, 4400 University Drive, Fairfax, VA 22030, USAThis paper presents optimized implementations of two different pipeline FFT processors on Xilinx Spartan-3 and Virtex-4 FPGAs. Different optimization techniques and rounding schemes were explored. The implementation results achieved better performance with lower resource usage than prior art. The 16-bit 1024-point FFT with the R22SDF architecture had a maximum clock frequency of 95.2 MHz and used 2802 slices on the Spartan-3, a throughput per area ratio of 0.034 Msamples/s/slice. The R4SDC architecture ran at 123.8 MHz and used 4409 slices on the Spartan-3, a throughput per area ratio of 0.028 Msamples/s/slice. On Virtex-4, the 16-bit 1024-point R22SDF architecture ran at 235.6 MHz and used 2256 slice, giving a 0.104 Msamples/s/slice ratio; the 16-bit 1024-point R4SDC architecture ran at 219.2 MHz and used 3064 slices, giving a 0.072 Msamples/s/slice ratio. The R22SDF was more efficient than the R4SDC in terms of throughput per area due to a simpler controller and an easier balanced rounding scheme. This paper also shows that balanced stage rounding is an appropriate rounding scheme for pipeline FFT processors.http://dx.doi.org/10.1155/2009/219140 |
| spellingShingle | Bin Zhou Yingning Peng David Hwang Pipeline FFT Architectures Optimized for FPGAs International Journal of Reconfigurable Computing |
| title | Pipeline FFT Architectures Optimized for FPGAs |
| title_full | Pipeline FFT Architectures Optimized for FPGAs |
| title_fullStr | Pipeline FFT Architectures Optimized for FPGAs |
| title_full_unstemmed | Pipeline FFT Architectures Optimized for FPGAs |
| title_short | Pipeline FFT Architectures Optimized for FPGAs |
| title_sort | pipeline fft architectures optimized for fpgas |
| url | http://dx.doi.org/10.1155/2009/219140 |
| work_keys_str_mv | AT binzhou pipelinefftarchitecturesoptimizedforfpgas AT yingningpeng pipelinefftarchitecturesoptimizedforfpgas AT davidhwang pipelinefftarchitecturesoptimizedforfpgas |